參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬(wàn)和333兆赫茲32位處理器）
文件頁(yè)數(shù)： 27/94頁(yè)
文件大小： 892K
代理商： PENTIUM II PROCESSOR
E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
27
Table 10. System Bus AC Specifications (Clock)
1, 2
T#
Parameter
Min
Nom
Max
Unit
Figure
Notes
System Bus Frequency
66.67
MHz
All processor core
frequencies
3
T1:
BCLK Period
15.0
ns
7
3, 4
T1B:
BCLK to Core Logic Offset
0.78
ns
6
Absolute Value
5, 6
T2:
BCLK Period Stability
±300
ps
7, 8
T3:
BCLK High Time
4.70
ns
7
@>1.8 V
T4:
BCLK Low Time
5.10
ns
7
@<0.7 V
T5:
BCLK Rise Time
0.75
1.95
ns
7
(0.7 V–1.8 V)
9
T6:
BCLK Fall Time
0.75
1.95
ns
7
(1.8 V–0.7 V)
9
NOTES:
1.
All AC timings for the GTL+ signals are referenced to the BCLK rising edge at 0.70 V at the processor edge fingers. This
reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to
receive the signal with a reference at 1.25 V. All GTL+ signal timings (address bus, data bus, etc.) are referenced at
1.00 V at the processor edge fingers.
All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.70 V at the processor edge fingers. This
reference is to account for trace length and capacitance on the processor substrate, allowing the processor core to
reference voltage of 1.25 V. All CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V at the
processor edge fingers.
The internal core clock frequency is derived from the System Bus clock. The System Bus clock to core clock ratio is
determined during initialization as described in Section 2.5. Table 11 shows the supported ratios for each processor.
The BCLK period allows a +0.5 ns tolerance for clock driver variation.
The BCLK offset time is the absolute difference needed between the BCLK signal rising edge arriving at the Slot 1 edge
finger at 0.7 V vs. arriving at the core logic at 1.25 V. The positive offset is needed to account for the delay between the
Slot 1 connector and processor core. The positive offset ensures both the processor core and the core logic receive the
BCLK edge concurrently.
See Section 3.1. for System Bus clock signal quality specifications.
Due to the difficulty of accurately measuring processor clock jitter in a system, it is recommended that a clock driver be
used that is designed to meet the period stability specification into a test load of 10 to 20 pF. This should be measured on
the rising edges of adjacent BCLKs crossing 1.25 V. The jitter present must be accounted for as a component of BCLK
timing skew between devices.
The clock driver’s closed loop jitter bandwidth must be set low to allow any PLL-based device to track the jitter created by
the clock driver. The -20 dB attenuation point of the clock driver, as measured into a 10 to 20 pF load, should be less than
500 kHz. This specification may be ensured by design and/or measured with a spectrum analyzer.
Not 100% tested. Specified by design/characterization as a clock driver requirement.
2.
3.
4.
5.
6.
7.
8.
9.
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