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| 型號： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 86/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
86
A.1.20
EMI
EMI pins should be connected to motherboard
ground and/or to chassis ground through zero ohm
(0
) resistors. The zero ohm resistors should be
placed in close proximity to the Slot 1 connector. The
path to chassis ground should be short in length and
have a low impedance.
A.1.21
FERR# (O)
The FERR# (Floating-point Error) signal is asserted
when the processor detects an unmasked floating-
point error. FERR# is similar to the ERROR# signal
on the Intel 387 coprocessor, and is included for
compatibility with systems using MS-DOS*-type
floating-point error reporting.
A.1.22
FLUSH# (I)
When the FLUSH# input signal is asserted,
processors write back all data in the Modified state
from their internal caches and invalidate all internal
cache lines. At the completion of this operation, the
processor issues a Flush Acknowledge transaction.
The processor does not cache any new data while
the FLUSH# signal remains asserted.
FLUSH# is an asynchronous signal. However, to
ensure recognition of this signal following an I/O write
instruction, it must be valid along with the TRDY#
assertion of the corresponding I/O Write bus
transaction.
On the active-to-inactive transition of RESET#, each
processor samples FLUSH# to determine its power-
on configuration. See the Pentium
II Processor
Developer’s Manual(Order Number 243341) for
details.
A.1.23
FRCERR (I/O)
If two processors are configured in a Functional
Redundancy Checking (FRC) master/checker pair,
as a single “l(fā)ogical” processor, the FRCERR
(Functional Redundancy Checking Error) signal is
asserted by the checker if a mismatch is detected
between the internally sampled outputs and the
master’s outputs. The checker’s FRCERR output pin
must be connected with the master’s FRCERR input
pin in this configuration.
For point-to-point connections, the checker always
compares against the master’s outputs. For bussed
single-driver signals, the checker compares against
the signal when the master is the only allowed driver.
For bussed multiple-driver wired-OR signals, the
checker compares against the signal only if the
master is expected to drive the signal low.
When a processor is configured as an FRC checker,
FRCERR is toggled during its reset action.
A checker asserts FRCERR for approximately
1 second after the active-to-inactive transition of
RESET# if it executes its Built-In Self-Test (BIST).
When BIST execution completes, the checker
processor deasserts FRCERR if BIST completed
successfully, and continues to assert FRCERR if
BIST fails. If the checker processor does not execute
the BIST action, then it keeps FRCERR asserted for
approximately 20 clocks and then deasserts it.
All asynchronous signals must be externally
synchronized to BCLK by system logic during FRC
mode operation.
A.1.24
HIT# (I/O), HITM# (I/O)
The HIT# (Snoop Hit) and HITM# (Hit Modified)
signals convey transaction snoop operation results,
and must connect the appropriate pins of all
Pentium II processor System Bus agents. Any such
agent may assert both HIT# and HITM# together to
indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
A.1.25
IERR# (O)
The IERR# (Internal Error) signal is asserted by a
processor as the result of an internal error. Assertion
of IERR# is usually accompanied by a SHUTDOWN
transaction on the Pentium II processor System Bus.
This transaction may optionally be converted to an
external error signal (e.g., NMI) by system core logic.
The processor will keep IERR# asserted until it is
handled in software, or with the assertion of
RESET#, BINIT#, or INIT#.
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