參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬(wàn)和333兆赫茲32位處理器）
文件頁(yè)數(shù)： 84/94頁(yè)
文件大小： 892K
代理商： PENTIUM II PROCESSOR
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
84
AP0# covers A[23:3]#. A correct parity signal is high
if an even number of covered signals are low and low
if an odd number of covered signals are low. This
allows parity to be high when all the covered signals
are high. AP[1:0]# should connect the appropriate
pins of all Pentium II processor System Bus agents.
A.1.6
BCLK (I)
The BCLK (Bus Clock) signal determines the bus
frequency. All Pentium II processor System Bus
agents must receive this signal to drive their outputs
and latch their inputs on the BCLK rising edge.
All external timing parameters are specified with
respect to the BCLK signal.
A.1.7
BERR# (I/O)
The BERR# (Bus Error) signal is asserted to indicate
an unrecoverable error without a bus protocol
violation. It may be driven by all Pentium II processor
System Bus agents, and must connect the
appropriate pins of all such agents, if used. However,
Pentium II processors do not observe assertions of
the BERR# signal.
BERR# assertion conditions are configurable at a
system level. Assertion options are defined by the
following options:
Enabled or disabled.
Asserted optionally for internal errors along with
IERR#.
Asserted optionally by the request initiator of a
bus transaction after it observes an error.
Asserted by any bus agent when it observes an
error in a bus transaction.
A.1.8
BINIT# (I/O)
The BINIT# (Bus Initialization) signal may be
observed and driven by all Pentium II processor
System Bus agents, and if used must connect the
appropriate pins of all such agents. If the BINIT#
driver is enabled during power on configuration,
BINIT# is asserted to signal any bus condition that
prevents reliable future information.
If BINIT# observation is enabled during power-on
configuration, and BINIT# is sampled asserted, all
bus state machines are reset and any data which
was in transit is lost. All agents reset their rotating ID
for bus arbitration to the state after reset, and internal
count information is lost. The L1 and L2 caches are
not affected.
If BINIT# observation is disabled during power-on
configuration, a central agent may handle an
assertion of BINIT# as appropriate to the Machine
Check Architecture (MCA) of the system.
A.1.9
BNR# (I/O)
The BNR# (Block Next Request) signal is used to
assert a bus stall by any bus agent who is unable to
accept new bus transactions. During a bus stall, the
current
bus
owner
cannot
transactions.
issue
any
new
Since multiple agents might need to request a bus
stall at the same time, BNR# is a wire-OR signal
which must connect the appropriate pins of all
Pentium II processor System Bus agents. In order to
avoid wire-OR glitches associated with simultaneous
edge transitions driven by multiple drivers, BNR# is
activated on specific clock edges and sampled on
specific clock edges.
A.1.10
BP[3:2]# (I/O)
The BP[3:2]# (Breakpoint) signals are outputs from
the processor that indicate the status of breakpoints.
A.1.11
BPM[1:0]# (I/O)
The BPM[1:0]# (Breakpoint Monitor) signals are
breakpoint and performance monitor signals. They
are outputs from the processor which indicate the
status of breakpoints and programmable counters
used for monitoring processor performance.
A.1.12
BPRI# (I)
The BPRI# (Bus Priority Request) signal is used to
arbitrate for ownership of the Pentium II processor
System Bus. It must connect the appropriate pins of
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