參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬(wàn)和333兆赫茲32位處理器）
文件頁(yè)數(shù)： 12/94頁(yè)
文件大?。?/td> 892K
代理商： PENTIUM II PROCESSOR
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
12
2.2.6.
DEEP SLEEP STATE — STATE 6
The Deep Sleep state is the lowest power state the
processor can enter while maintaining context. The
Deep Sleep state is entered by stopping the BCLK
input (after the Sleep state was entered from the
assertion of the SLP# pin). The processor is in Deep
Sleep state immediately after the BCLK is stopped. It
is recommended that the BCLK input be held low
during the Deep Sleep state. Stopping of the BCLK
input lowers the overall current consumption to
leakage levels.
To re-enter the Sleep state, the BCLK input must be
restarted. A period of 1 ms (to allow for PLL
stabilization) must occur before the processor can be
considered to be in the Sleep state.
While in Deep Sleep state, the processor is
incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions
of signals are allowed on the System Bus while the
processor is in Deep Sleep state. Any transition on
an input signal before the processor has returned to
Stop-Grant state will result in unpredictable behavior.
2.2.7.
CLOCK CONTROL AND LOW POWER
MODES
The processor provides the clock signal to the L2
cache. During AutoHALT Power Down and Stop-
Grant states, the processor will process the snoop
phase of a System Bus cycle. The processor will not
stop the clock data to the L2 cache during AutoHALT
Power Down or Stop-Grant states. Entrance into the
HALT/Grant Snoop state will allow the L2 cache to
be snooped, similar to Normal state.
When the processor is in Sleep and Deep Sleep
states, it will not respond to interrupts or snoop
transactions. During Sleep state, the clock to the L2
cache is not stopped. During the Deep Sleep state,
the clock to the L2 cache is stopped. The clock to the
L2 cache will be restarted only after the internal
clocking mechanism for the processor is stable (i.e.,
the processor has re-entered Sleep state).
The PICCLK should not be removed during the
AutoHALT Power Down or Stop-Grant states. The
PICCLK can be removed during the Sleep or Deep
Sleep states. When transitioning from the Deep
Sleep to Sleep states, the PICCLK must be restarted
with the BCLK.
2.3.
Power and Ground Pins
As future versions of Pentium II processors are
released, the operating voltage of the processor core
and of the L2 cache die may differ from each other.
There are two groups of power inputs on the
Pentium II processor package to support the possible
voltage difference between the two components in
the package. There are also five pins defined on the
package for voltage identification (VID). These pins
specify the voltage required by the processor core.
These have been added to cleanly support voltage
specification variations on current and future
Pentium II processors.
For clean on-chip power distribution, Pentium II
processors have 27 V
CC
(power) and 30 V
SS
(ground) inputs. The 27 V
CC
pins are further divided
to provide the different voltage levels to the
components. Vcc
CORE
inputs for the processor core
and some L2 cache components account for 19 of
the V
CC
pins, while 4 V
TT
inputs (1.5 V) are used to
provide a GTL+ termination voltage to the processor
and 3 Vcc
L2
inputs (3.3 V) are for use by the L2
cache TagRAM and BSRAMs. One Vcc
5
pin is
provided for use by the Slot 1 Test Kit. Vcc
5
, Vcc
L2
,
and Vcc
CORE
must remain electrically separated from
each other. On the circuit board, all Vcc
CORE
pins
must be connected to a voltage island and all Vcc
L2
pins must be connected to a separate voltage island
(an island is a portion of a power plane that has been
divided, or an entire plane). Similarly, all V
SS
pins
must be connected to a system ground plane.
2.4.
Decoupling Guidelines
Due to the large number of transistors and high
internal clock speeds, the processor is capable of
generating large average current swings between
low and full power states. This causes voltages on
power planes to sag below their nominal value if bulk
decoupling is not adequate. Care must be taken in
the board design to ensure that the voltage provided
to the processor remains within the specifications
listed in this document. Failure to do so can result in
timing violations or a reduced lifetime of the
component.
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