參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器）
文件頁數(shù)： 29/94頁
文件大?。?/td> 892K
代理商： PENTIUM II PROCESSOR
E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
29
Table 13. System Bus AC Specifications (CMOS Signal Group)
1, 2, 3
T#
Parameter
Min
Max
Unit
Figure
Notes
T11:
2.5 V Output Valid Delay
1.00
10.5
ns
8
4
T12:
2.5 V Input Setup Time
5.50
ns
9
5, 6
T13:
2.5 V Input Hold Time
1.75
ns
9
5
T14:
2.5 V Input Pulse Width,
except PWRGOOD
2
BCLKs
8
Active and Inactive
states
T15:
PWRGOOD Inactive Pulse
Width
10
BCLKs
8
13
7
NOTES:
1.
2.
Not 100% tested. Specified by design characterization.
All AC timings for the CMOS signals are referenced to the BCLK rising edge at 0.7 V at the processor edge fingers. All
CMOS signal timings (address bus, data bus, etc.) are referenced at 1.25 V at the processor edge fingers.
These signals may be driven asynchronously, but must be driven synchronously in FRC mode.
Valid delay timings for these signals are specified to 2.5 V +5%.. See Table 3 for pull-up resistor values.
To ensure recognition on a specific clock, the setup and hold times with respect to BCLK must be met.
INTR and NMI are only valid during APIC disable mode. LINT[1:0]# are only valid during APIC enabled mode.
When driven inactive or after Vcc
CORE
, Vcc
L2
and BCLK become stable.
3.
4.
5.
6.
7.
Table 14. System Bus AC Specifications (Reset Conditions)
T#
Parameter
Min
Max
Unit
Figure
Notes
T16:
Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Setup Time
4
BCLKs
11
Before deassertion of
RESET#
T17:
Reset Configuration Signals
(A[14:5]#, BR0#, FLUSH#,
INIT#) Hold Time
2
20
BCLKs
11
After clock that
deasserts RESET#
T18:
Reset Configuration Signals
(A20M#, IGNNE#,
LINT[1:0]#) Setup Time
1
ms
12
Before deassertion of
RESET#
T19:
Reset Configuration Signals
(A20M#, IGNNE#,
LINT[1:0]#) Delay Time
5
BCLKs
12
After assertion of
RESET#
1
T20:
Reset Configuration Signals
(A20M#, IGNNE#,
LINT[1:0]#) Hold Time
2
20
BCLKs
12
11
After clock that
deasserts RESET#
NOTE:
1.
For a Reset, the clock ratio defined by these signals must be a safe value (their final or lower multiplier) within this delay
unless PWRGOOD is being driven inactive.
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