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| 型號： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 18/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
18
2.7.
Pentium
II Processor System
Bus Unused Pins
All RESERVED pins must remain unconnected.
Connection of Reserved pins to Vcc
CORE
, Vcc
L2
, V
SS
or to any signal can result in component malfunction
or incompatibility with future Slot 1 products. See
Section 5.2. for a pin listing of the processor and the
location of each Reserved pin.
All TESTHI pins must be connected to 2.5 V via a
pull-up resistor of between 1 and 10 K
value.
PICCLK must be driven with a valid clock input and
the PICD[1:0] lines must be pulled-up to 2.5 V even
when the local APIC will not be used. A separate
pull-up resistor must be provided for each PICD line
(see Table 3 for recommended values).
Table 3. Recommended Pull-Up Resistor
Values (Approximate) for CMOS Signals
1, 2, 3
Recommended
Resistor Value
(Approximate)
CMOS Signal
150
TDO, TMS, PICD[0]#,
PICD[1]#
150 – 220
FERR#, IERR#, THERMTRIP#
150 – 330
A20M#, IGNNE#, INIT#,
LINT[1]/NMI, LINT[0]/INTR,
PWRGOOD, SLP#, PREQ#,
TDI
410
STPCLK#, SMI#
500
FLUSH#
NOTES:
1.
These resistor values are recommended for system
implementations using open drain CMOS buffers.
These approximate resistor values are for proper
operation of debug tools only A ~150
pull-up resistor
is expected for these signals.
The TRST# signal must be driven low at power on
reset. This can be accomplished with a 680
pull-
down resistor.
2.
3.
For reliable operation, always connect unused inputs
or bi-directional signals to an appropriate signal level.
Unused GTL+ inputs should be left as no connects;
GTL+ termination is provided on the processor.
Unused active low CMOS inputs should be
connected to 2.5V. Unused active high inputs should
be connected to ground (V
SS
). Unused outputs can
be left unconnected. A resistor must be used when
tying bi-directional signals to power or ground. When
tying any signal to power or ground, a resistor will
also allow for system testability. For unused pins, it is
suggested that
～
10 K
resistors be used for pull-ups
(except for PICD[1:0] as discussed above) and
～
1 K
resistors be used for pull-downs.
2.8.
Pentium
II Processor System
Bus Signal Groups
In order to simplify the following discussion, the
Pentium II processor System Bus signals have been
combined into groups by buffer type.
All Pentium II
processor System Bus outputs are open drain
and require a high-level source provided externally
by the termination or pull-up resistor.
GTL+ input signals have differential input buffers,
which use V
REF
as a reference signal. GTL+ output
signals require termination to 1.5 V. In this document,
the term “GTL+ Input” refers to the GTL+ input group
as well as the GTL+ I/O group when receiving.
Similarly, “GTL+ Output” refers to the GTL+ output
group as well as the GTL+ I/O group when driving.
EMI pins should be connected to motherboard
ground and/or to chassis ground through zero ohm
(0
)
resistors. The zero ohm resistors should be
placed in close proximity to the Slot 1 connector. The
path to chassis ground should be short in length and
have a low impedance.
The CMOS, Clock, APIC and JTAG inputs can each
be driven from ground to 2.5 V. The CMOS, APIC
and JTAG outputs are open drain and should be
pulled high to 2.5 V. This ensures not only correct
operation
for
the
Pentium II
compatibility for future Slot 1 products as well. See
Table 3 for recommended pull-up resistor values on
each CMOS signal. 150
resistors are expected on
the PICD[1:0] lines. Other values in Table 3 are
specified for proper logic analyzer and test mode
operation only.
processor,
but
The groups and the signals contained within each
group are shown in Table 4. Refer to Appendix A for
descriptions of these signals.
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