參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬(wàn)和333兆赫茲32位處理器）
文件頁(yè)數(shù)： 87/94頁(yè)
文件大?。?/td> 892K
代理商： PENTIUM II PROCESSOR
E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
87
A.1.26
IGNNE# (I)
The IGNNE# (Ignore Numeric Error) signal is
asserted to force the processor to ignore a numeric
error and continue to execute noncontrol floating-
point instructions. If IGNNE# is deasserted, the
processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point
instruction caused an error. IGNNE# has no effect
when the NE bit in control register 0 is set.
IGNNE# is an asynchronous signal. However, to
ensure recognition of this signal following an I/O write
instruction, it must be valid along with the TRDY#
assertion of the corresponding I/O Write bus
transaction.
During active RESET#, the Pentium II processor
begins sampling the A20M#, IGNNE#, and LINT[1:0]
values to determine the ratio of core-clock frequency
to bus-clock frequency. (See Table 1.) On the active-
to-inactive transition of RESET#, the Pentium II
processor latches these signals and freezes the
frequency ratio internally. System logic must then
release these signals for normal operation; Figure 6
for an example implementation of this logic.
A.1.27
INIT# (I)
The INIT# (Initialization) signal, when asserted,
resets integer registers inside all processors without
affecting their internal (L1 or L2) caches or floating-
point registers. Each processor then begins
execution at the power-on reset vector configured
during power-on configuration. The processor
continues to handle snoop requests during INIT#
assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all Pentium II
processor System Bus agents.
If INIT# is sampled active on the active to inactive
transition of RESET#, then the processor executes
its Built-In Self-Test (BIST).
A.1.28
LINT[1:0] (I)
The LINT[1:0] (Local APIC Interrupt) signals must
connect the appropriate pins of all APIC Bus agents,
including all processors and the core logic or I/O
APIC component. When the APIC is disabled, the
LINT0 signal becomes INTR, a maskable interrupt
request signal, and LINT1 becomes NMI, a
nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured
via BIOS programming of the APIC register space to
be used either as NMI/INTR or LINT[1:0]. Because
the APIC is enabled by default after reset, operation
of these pins as LINT[1:0] is the default configuration.
During active RESET#, the Pentium II processor
begins sampling the A20M#, IGNNE#, and LINT[1:0]
values to determine the ratio of core-clock frequency
to bus-clock frequency. (See Table 1.) On the active-
to-inactive transition of RESET#, the Pentium II
processor latches these signals and freezes the
frequency ratio internally. System logic must then
release these signals for normal operation; see
Figure 6 for an example implementation of this logic.
A.1.29
LOCK# (I/O)
The LOCK# signal indicates to the system that a
transaction must occur atomically. This signal must
connect the appropriate pins of all Pentium II
processor System Bus agents. For a locked
sequence of transactions, LOCK# is asserted from
the beginning of the first transaction end of the last
transaction.
When the priority agent asserts BPRI# to arbitrate for
ownership of the Pentium II processor System Bus, it
will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the
Pentium II processor System Bus throughout the bus
locked operation and ensure the atomicity of lock.
A.1.30
PICCLK (I)
The PICCLK (APIC Clock) signal is an input clock to
the processor and core logic or I/O APIC which is
required for operation of all processors, core logic,
and I/O APIC components on the APIC bus. During
FRC mode operation, PICCLK must be of (and
synchronous to) BCLK.
相關(guān)PDF資料
PDF描述
pentium II xeon processor pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器)
Pentium III cpu with mobile Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動(dòng)模塊連接器2奔III處理器)
pentium III CPU Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器)
pentium III processor 32 bit Processor Mobile Module(32 位帶移動(dòng)模塊處理器)
Pentium OverDrive Processor Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術(shù)奔騰超速轉(zhuǎn)動(dòng)處理器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
P-ENV568K3G3 制造商:Panasonic Industrial Company 功能描述:TUNER
PEO14012 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC
PEO14024 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC
PEO96742 制造商:Delphi Corporation 功能描述:ASM TERM
PEOODO3A 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*