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| 型號(hào)： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 13/94頁 |
| 文件大小： | 892K |
| 代理商： | PENTIUM II PROCESSOR |
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E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
13
Regulator solutions need to provide bulk capacitance
with a low Effective Series Resistance (ESR) and
keep an interconnect resistance from the regulator
(or VRM pins) to the Slot 1 connector of less than
0.5 m
. This can be accomplished by keeping a
maximum distance of 1.5 inches between the
regulator output and Slot 1 connector. The
recommended Vcc
CORE
interconnect is a 2.0 inch
wide (the width of the VRM connector) by 1.5 inch
long (maximum distance between the Slot 1
connector and the VRM connector) plane segment
with a standard 1-ounce plating. Bulk decoupling for
the large current swings when the processor is
powering on, or entering/exiting low power states, is
provided on the voltage regulation module (VRM)
defined in the Pentium
II ProcessorPower
Distribution Guidelines. The Vcc
CORE
input should be
capable of delivering a recommended minimum
dIcc
CORE
/dt (defined in Table 6) while maintaining the
tolerances (also defined in Table 6).
2.4.1.
SYSTEM BUS GTL+ DECOUPLING
The Pentium II processor contains high frequency
decoupling capacitance on the processor substrate;
however, bulk decoupling must be provided for by
the system motherboard for proper GTL+ bus
operation. See AP-585, Pentium
II Processor GTL+
Guidelines
(Order
Number
Pentium
II Processor Power Distribution Guidelines
(Order Number 243332); and Pentium
II Processor
Developer’s Manual(Order Number 243341) for
more information.
243330);
AP-587,
2.5.
Pentium
II Processor System
Bus Clock and Processor
Clocking
The BCLK input directly controls the operating speed
of the Pentium II Processor System Bus interface. All
Pentium II Processor System Bus timing parameters
are specified with respect to the rising edge of the
BCLK
input.
The
Pentium II
frequency must be configured during Reset by using
the A20M#, IGNNE#, LINT[1]/NMI and LINT[0]/INTR
pins. (See Table 1.) The value on these pins during
Reset determines the multiplier that the PLL will use
for the internal core clock. See the Pentium
II
Processor Developer’s Manual(Order Number
processor
core
243341) for the definition of these pins during Reset
and the operation of the pins after Reset.
See Figure 4 for the timing relationship between the
System Bus multiplier signals, RESET#, CRESET#
and normal processor operation. Table 1 is a list of
multipliers supported. All other multipliers are not
authorized or supported.
Using CRESET# (CMOS reset on the baseboard),
the circuit in Figure 5 can be used to share these
configuration signals. The component used as the
multiplexer must not have outputs that drive higher
than 2.5 V in order to meet the Pentium II processor’s
2.5 V tolerant buffer specifications. The multiplexer
output current should be limited to 200 mA maximum,
in case the Vcc
CORE
supply to the processor ever
fails.
As shown in Figure 4, the pull-up resistors between
the multiplexer and the processor (330
) force a
ratio of into the processor in the event that the
Pentium II
processor
powers
multiplexer and/or the core logic. This prevents the
processor from ever seeing a ratio higher than the
final ratio.
up
before
the
If the multiplexer were powered by Vcc
2.5
, a pull-
down could be used on CRESET# instead of the four
pull-up resistors between the multiplexer and the
Pentium II processor. In this case, the multiplexer
must be designed such that the compatibility inputs
are truly ignored, as their state is unknown.
The compatibility inputs to the multiplexer must meet
the input specifications of the multiplexer. This may
require a level translation before the multiplexer
inputs unless the inputs and the signals driving them
are already compatible.
For FRC mode operation, the multiplexer will need to
be clocked using BCLK to meet setup and hold times
to the processors. This may require the use of high
speed programmable logic.
Multiplying the bus clock frequency is required to
increase performance while allowing for cost
effective distribution of signals within a system. The
System Bus frequency multipliers supported are
shown in Table 11;
other combinations will not be
validated
nor
are
implementation
.
they
authorized
for
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