參數(shù)資料
型號(hào)： pentium II processor
廠商： Intel Corp.
英文描述： 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器)
中文描述： 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬(wàn)和333兆赫茲32位處理器）
文件頁(yè)數(shù)： 26/94頁(yè)
文件大?。?/td> 892K
代理商： PENTIUM II PROCESSOR
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
E
26
2.12.
GTL+ System Bus
Specifications
It is recommended to have the GTL+ bus routed in a
daisy-chain fashion with termination resistors at each
end of every signal trace. These termination resistors
are placed electrically between the ends of the signal
traces and the V
TT
voltage supply and generally are
chosen to approximate the substrate impedance. The
valid high and low levels are determined by the input
buffers using a reference voltage called V
REF
.
Table 9 lists the nominal specification for the GTL+
termination voltage (V
TT
). The GTL+ reference
voltage (V
REF
) should be set to 2/3 V
TT
for the core
logic using a voltage divider on the motherboard. It is
important that the motherboard impedance be
specified and held to a ±20% tolerance, and that the
intrinsic trace capacitance for the GTL+ signal group
traces is known. For more details on GTL+, see the
Pentium
II Processor Developer’s Manual (Order
Number 243341) and the Pentium
II Processor
GTL+ Guidelines(Order Number 243330).
2.13.
Pentium
II Processor System
Bus AC Specifications
The System Bus timings specified in this section are
defined at the processor edge fingers. Timings will be
tested at the processor core during manufacturing.
Timings at the processor edge fingers will be
specified by design characterization.
See Appendix A for the Pentium II processor edge
finger signal definitions.
Table 10 through Table 15 list the AC specifications
associated with the Pentium II processor System
Bus. The System Bus AC specifications are broken
into the following categories: Table 10 and Table 11
contain the System Bus clock core frequency and
Cache Bus frequencies; Table 12 contains the GTL+
specifications Table 13 contains the CMOS signal
group specifications; Table 14 contains timings for
the reset conditions; Table 15 covers APIC bus
timing; Table 16 covers TAP timing.
All System Bus AC specifications for the GTL+ signal
group are relative to the rising edge of the BCLK
input. All GTL+ timings are referenced to V
REF
for
both ‘0’ and ‘1’ logic levels unless otherwise
specified.
The timings specified in this section should be used
in conjunction with the I/O buffer models provided by
Intel. These I/O buffer models, which include
package information, are available in IBIS format on
Intel’s Web site: “http://www.intel.com”. GTL+ layout
guidelines are also available in AP-585, Pentium
II
Processor GTL+ Guidelines(Order Number 243330).
Care should be taken to read all notes associated
with a particular timing parameter.
Table 9. Pentium
II Processor GTL+ Bus Specifications
1
Symbol
Parameter
Min
Typ
Max
Units
Notes
V
TT
Bus Termination Voltage
1.365
1.5
1.635
V
1.5 V ±3%, ±9%
2
R
TT
Termination Resistor
56
Ohms
±5%
V
REF
Bus Reference Voltage
2/3 V
TT
V
±2%
3
NOTES:
1.
The Pentium
II processor contains GTL+ termination resistors at the end of the signal trace on the processor substrate.
The Pentium II processor generates V
REF
, on the processor, by using a voltage divider on V
TT
supplied through the Slot 1
connector.
V
must be held to 1.5 V ±9%; dIcc
Vtt
/dt is specified in Table 6. It is recommended that V
TT
be held to 1.5 ±3% during
System Bus idle.
V
REF
is generated by the processor to be 2/3 V
TT
nominally.
2.
3.
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