- 您現(xiàn)在的位置：買賣IC網 > PDF目錄369993 > pentium II processor (Intel Corp.) 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) PDF資料下載
參數(shù)資料
| 型號： | pentium II processor |
| 廠商： | Intel Corp. |
| 英文描述： | 32 bit processor AT 233MHZ，266MHZ，300MHZ and 333MHZ(工作頻率233，266，300和333兆赫茲32位處理器) |
| 中文描述： | 32位處理器，233MHZ，266MHz的的300MHz和333MHz的（工作頻率23326.63萬和333兆赫茲32位處理器） |
| 文件頁數(shù)： | 83/94頁 |
| 文件大?。?/td> | 892K |
| 代理商： | PENTIUM II PROCESSOR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁當前第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁
E
PENTIUM II PROCESSOR AT 233 MHZ, 266 MHZ, 300 MHZ, AND 333 MHZ
83
APPENDIX A
This appendix provides an alphabetical listing of all
Pentium II processor signals. The tables at the end of
this appendix summarize the signals by direction:
output, input, and I/O.
A.1
ALPHABETICAL SIGNALS
REFERENCE
A.1.1
A[35:0]# (I/O)
The A[35:3]# (Address) signals define a 2
36
-byte
physical memory address space. When ADS# is
active, these pins transmit the address of a
transaction; when ADS# is inactive, these pins
transmit transaction type information. These signals
must connect the appropriate pins of all agents on
the Pentium II processor System Bus. The A[35:24]#
signals are parity-protected by the AP1# parity
signal, and the A[23:3]# signals are parity-protected
by the AP0# parity signal.
On the active-to-inactive transition of RESET#, the
processors sample the A[35:3]# pins to determine
their power-on configuration. See the Pentium
II
Processor Developer’s Manual(Order Number
243341) for details.
A.1.2
A20M# (I)
If the A20M# (Address-20 Mask) input signal is
asserted, the Pentium II processor masks physical
address bit 20 (A20#) before looking up a line in any
internal cache and before driving a read/write
transaction on the bus. Asserting A20M# emulates
the 8086 processor’s address wrap-around at the
1-Mbyte boundary. Assertion of A20M# is only
supported in real mode.
A20M# is an asynchronous signal. However, to
ensure recognition of this signal following an I/O write
instruction, it must be valid along with the TRDY#
assertion of the corresponding I/O Write bus
transaction.
During active RESET#, each processor begins
sampling the A20M#, IGNNE# , and LINT[1:0] values
to determine the ratio of core-clock frequency to bus-
clock frequency. (See Table 1.) On the active-to-
inactive transition of RESET#, each processor
latches these signals and freezes the frequency ratio
internally. System logic must then release these
signals for normal operation; see Figure 6 for an
example implementation of this logic.
A.1.3
ADS# (I/O)
The ADS# (Address Strobe) signal is asserted to
indicate the validity of the transaction address on the
A[35:3]# pins. All bus agents observe the ADS#
activation to begin parity
checking, address decode, internal snoop, or
deferred reply ID match operations associated with
the new transaction. This signal must connect the
appropriate pins on all Pentium II processor System
Bus agents.
checking,
protocol
A.1.4
AERR# (I/O)
The AERR# (Address Parity Error) signal is
observed and driven by all Pentium II processor
System Bus agents, and if used, must connect the
appropriate pins on all Pentium II processor System
Bus agents. AERR# observation is optionally
enabled during power-on configuration; if enabled, a
valid assertion of AERR# aborts the current
transaction.
If AERR# observation is disabled during power-on
configuration, a central agent may handle an
assertion of AERR# as appropriate to the Machine
Check Architecture (MCA) of the system.
A.1.5
AP[1:0]# (I/O)
The AP[1:0]# (Address Parity) signals are driven by
the request initiator along with ADS#, A[35:3]#,
REQ[4:0]#, and RP#. AP1# covers A[35:24]#, and
相關PDF資料 |
PDF描述 |
|---|---|
| pentium II xeon processor | pentium II xeon processor at 400 and 450 MHZ(工作頻率400和450兆赫茲奔II處理器) |
| Pentium III cpu with mobile | Pentium III processor Mobile Module Connector 2 (MMC-2)(帶移動模塊連接器2奔III處理器) |
| pentium III CPU | Pentium III Processor for the SC242 at 450MHz to 1.0GHz(SC242工作頻率450MHZ到1GHZ奔III處理器) |
| pentium III processor | 32 bit Processor Mobile Module(32 位帶移動模塊處理器) |
| Pentium OverDrive Processor | Pentium OverDrive Processor With MMX Technology For Pentium Processor-Based System(帶MMX技術奔騰超速轉動處理器) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| P-ENV568K3G3 | 制造商:Panasonic Industrial Company 功能描述:TUNER |
| PEO14012 | 制造商:TE Connectivity 功能描述:RELAY SPCO 12VDC |
| PEO14024 | 制造商:TE Connectivity 功能描述:RELAY SPCO 24VDC |
| PEO96742 | 制造商:Delphi Corporation 功能描述:ASM TERM |
| PEOODO3A | 制造商:MACOM 制造商全稱:Tyco Electronics 功能描述:Versatile Power Entry Module with Small Footprint |
發(fā)布緊急采購，3分鐘左右您將得到回復。