Pentium
II Processor – Low-Power Module
Datasheet
7
1.0
Introduction
The Pentium
II Processor – Low-Power Module is a fundamental building block for a system
manufacturer to incorporate into a system. The Pentium II Processor – Low-Power Module
incorporates a Pentium II processor –Low Power core, second-level cache with Tag RAM, Intel
443BX Host Bridge/Controller (Northbridge), voltage regulator, and an SMBus thermal sensor on
a single printed circuit board.
Intel’s host bridge architecture allows for physical partitioning at the PCI, AGP and DRAM
interfaces; therefore the electrical interconnect defined for the module includes the PCI bus, AGP
bus, DRAM memory bus and some host bridge sideband signals. An onboard voltage regulator
provides the DC conversion from the system manufacturer’s system DC voltage to the processor’s
core and I/O voltage. This isolation of the processor voltage requirements allows the system
manufacturer to incorporate Low-Power Modules with different processor variants into a single
system.
Building around this modular design gives the system manufacturer these advantages:
Avoids complexities associated with designing high-speed processor core logic boards
Provides an upgrade path from previous modules for designs using a standard interface
This document provides the technical information required to assist the OEM in developing the
latest systems for the applied computing market segment.
1.1
Module Terminology
The following terms are used often in this document and are explained here for clarification:
Pentium II processor – Low Power—
The central processing unit including cache components.
Processor core—
The processor’s execution engine.
Thermal Transfer Plate (TTP)—
The surface used by the OEM to attach a system level thermal
solution to the Pentium II Processor – Low-Power Module.
Thermal Design Power (TDP)—
The typical power consumed by the CPU while executing a
standard application.
2.0
Architecture Overview
The Pentium II Processor – Low-Power Module is a small, highly integrated assembly containing
the Pentium II processor –Low Power core with internal/bus frequencies of 266/66 MHz and its
immediate system-level support. The module interfaces electrically to its host system via a 3.3 V
PCI bus, a 3.3 V AGP bus, a 3.3 V memory bus and the Intel 443BX Host Bridge/Controller.
The module includes a second-level cache of pipeline burst SRAM supporting up to 512 Kbytes.
The ZZ “snooze” mode power management featured in previous modules is not supported. Instead
it supports the “Stop Clock” mode of power management for the L2 SRAMs. In this mode, the
clock signals to the L2 SRAMs are stopped or “parked” in a low power state by the processor.