參數(shù)資料
型號(hào): Pentium II 266
廠商: Intel Corp.
英文描述: 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述: 32位處理器低功率模塊(帶低能量模塊的32位處理器)
文件頁(yè)數(shù): 15/50頁(yè)
文件大?。?/td> 1003K
代理商: PENTIUM II 266
Pentium
II Processor – Low-Power Module
Datasheet
15
3.1.6
Power Management/Geyserville (11 Signals)
Table 6
lists the module’s Power Management signals. The SM_CLK and SM_DATA signals refer
to the two-wire serial SMBus interface. Although this interface is currently used solely for the
digital thermal sensor thermal sensor, there are reserved serial addresses for future use. See “Active
Thermal Feedback” on page 37 for more details.
A20M#
I D
CMOS
V_CPUPU
Address Bit 20 Mask:
When enabled, this open drain signal
causes the processor to emulate the address wraparound at one
Mbyte which occurs on the Intel 8086 processor.
SMI#
I D
CMOS
V_CPUPU
System Management Interrupt:
SMI# is an active low
synchronous output from the PIIX4E that is asserted in response
to one of many enabled hardware or software events.
The SMI#
open drain signal can be an asynchronous input to the processor.
However, in this chip set SMI# is synchronous to PCLK.
STPCLK#
I D
CMOS
V_CPUPU
Stop Clock:
STPCLK# is an active low synchronous open drain
output from the PIIX4E that is asserted in response to one of many
hardware or software events.
STPCLK# connects directly to the
processor and is synchronous to PCICLK.
When the processor
samples STPCLK# asserted it responds by entering a low power
state (Quick Start). The processor will only exit this mode when
this signal is de-asserted.
Table 5. Processor/PIIX4E Sideband Signal Descriptions (Sheet 2 of 2)
Name
Type
Voltage
Description
Table 6. Power Management/Geyserville Signal Descriptions (Sheet 1 of 2)
Name
Type
Voltage
Description
SUS_STAT1#
I
CMOS
V_3ALWAYS
Suspend Status:
This signal connects to the
SUS_STAT1# output of PIIX4E. It provides information on
host clock status and is asserted during all suspend
states.
VR_ON
I
CMOS
V_3S
VR_ON:
Voltage regulator ON.
This 3.3 V (5 V tolerant)
signal controls the operation of the module’s voltage
regulator.
VR_ON should be generated as a function of
the PIIX4E SUSB# signal which is used for controlling the
“Suspend State B” voltage planes.
VR_PWRGD
O
V_3S
VR_PWRGD:
This signal is driven high by the to indicate
the voltage regulator is stable and is pulled low using a
131.6K resistor when inactive.
It can be used in some
combination to generate the system PWRGOOD signal.
BXPWROK
I
CMOS
V_3
Power OK to BX:
This signal must go active 1mS after
the V_3 power rail is stable.
SM_CLK
I/O D
CMOS
V_3
Serial Clock:
This clock signal is used on the SMBUS
interface to the digital thermal sensor.
SM_DATA
I/O D
CMOS
V_3
Serial Data:
Open-drain data signal on the SMBUS
interface to the digital thermal sensor.
ATF_INT#
O D
CMOS
V_3
ATF Interrupt:
This signal is an open-drain output signal
of the digital thermal sensor.
V_3ALWAYS: 3.3 V voltage supply. It is generated whenever V_DC is available and supplied to the
PIIX4E resume well.
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