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參數(shù)資料
| 型號： | Pentium II 266 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器) |
| 中文描述： | 32位處理器低功率模塊（帶低能量模塊的32位處理器） |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | PENTIUM II 266 |
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Pentium
II Processor – Low-Power Module
18
Datasheet
3.1.9
ITP/JTAG (9 Signals)
Table 9
lists the module’s ITP/JTAG signals, which the system electronics can use to implement a
JTAG chain and ITP port, if desired.
3.1.10
Miscellaneous (82 Signals)
Table 10 lists the module’s miscellaneous signal pins.
Table 9. ITP/JTAG Pins
Name
Type
Voltage
Description
TDO
O
V_CPUPU
JTAG Test Data Out:
Serial output port. TAP instructions and data
are shifted out of the processor from this port.
TDI
I
V_CPUPU
JTAG Test Data In:
Serial input port. TAP instructions and data are
shifted into the processor from this port.
TMS
I
V_CPUPU
JTAG Test Mode Select:
Controls the TAP controller change
sequence.
TCLK
I
V_CPUPU
JTAG Test Clock:
Testability clock for clocking the JTAG boundary
scan sequence.
TRST#
I
V_CPUPU
JTAG Test Reset:
Asynchronously resets the TAP controller in the
processor.
FS_RESET#
O
GTL+
Processor Reset:
Processor reset status to the ITP.
VTT
O
V_Core
GTL+ Termination Voltage:
Used by the POWERON pin on the ITP
debug port to determine when target system is on. POWERON pin is
pulled up using a 1 K
resistor to VTT.
FS_PREQ#
I
V_CPUPU
Debug Mode Request:
Driven by the ITP - makes request to enter
debug mode.
FS_PRDY#
O
GTL+
Debug Mode Ready:
Driven by the processor - informs the ITP that
the processor is in debug mode.
NOTE:
Recommendation: DBREST# (reset target system) on the ITP debug port can be “l(fā)ogically AND’ed”
with the signal VR_PWRGD and connected to the PIIX4E input PWROK.
Table 10. Miscellaneous Pins
Name
Type
Number
Description
Module ID[3:0]
O
CMOS
4
Module Revision ID:
These pins track the revision level of the
processor module. A 100 K
pull up resistor to V_3S is required
on these signals and to be placed on the system electronics for
these signals.
Ground
I
45
Ground
Reserved
RSVD
33
Unallocated
Reserved
pins and should not be connected.
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