參數(shù)資料
型號： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁數(shù)： 37/50頁
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
Datasheet
37
4.7
Active Thermal Feedback
Table 21 identifies the address allocated for the System Management Bus (SMBus) thermal sensor
used on the module.
4.8
Power Management
4.8.1
Clock Control Architecture
The processor clock control architecture (Figure 9) has been optimized for leading edge deep green
system designs. The Auto Halt state provides a low power clock state that can be controlled
through the software execution of the HLT instruction. The Quick Start state provides a very low
power, low exit latency clock state that can be used for hardware controlled “idle” computer states.
The Deep Sleep state provides an extremely low power state that can be used for “Power-on
Suspend” computer states, which is an alternative to shutting off the processor’s power. Compared
to the Pentium processor exit latency of 1 ms, the exit latency of the Deep Sleep state has been
reduced to 30 μs in the Pentium II processor – Low Power. The Stop Grant and Sleep states shown
in Figure 9 are intended for use in “Deep Green” desktop and server systems—not in applied
computing systems. Performing state transitions not shown in Figure 9 is neither recommended nor
supported.
The clock control architecture consists of seven different clock states: Normal, Stop Grant, Auto
Halt, Quick Start, HALT/Grant Snoop, Sleep and Deep Sleep states. The Stop Grant and Quick
Start clock states are mutually exclusive, i.e., a strapping option on pin A15# chooses which state is
entered when the STPCLK# signal is asserted. The Quick Start state is enabled by strapping the
A15# pin to ground at Reset; otherwise, asserting the STPCLK# signal puts the processor into the
Stop Grant state. The Stop Grant state has a higher power level than the Quick Start state and is
designed for SMP platforms. The Quick Start state has a much lower power level, but it can only be
used in uniprocessor platforms. Table 24 provides clock state characteristics (power numbers based
on estimates for a Pentium II Processor – Low Power running at 266 MHz), which are described in
detail in the following sections.
Table 21. Thermal Sensor SMBUS Address
Function
Fixed Address AD Bits (6:4)
Selectable Address AD Bits (3:0)
Thermal Sensor
100
1110
Reserved
010
1010
Reserved
010
1011
NOTE:
The thermal sensor used is compliant with SMBus addressing. Please refer to the Pentium
II
processor Thermal Sensor Interface Specification
Table 22. New Pins in the Pentium
II
Processor – Low Power
Pin Name
Type
Description
SMBALERT#
O
Thermal sensor attention signal.
SMBCLK
I/O
SMBus clock signal.
Refer to the System Management Bus Specificationfor
descriptions and specifications of the three SMBus signals.
SMBDATA
I/O
SMBus data signal.
Refer to the System Management Bus Specificationfor
descriptions and specifications of the three SMBus signals.
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