參數(shù)資料
型號(hào)： Pentium II 266
廠(chǎng)商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁(yè)數(shù)： 41/50頁(yè)
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
Datasheet
41
4.8.5
HALT/GRANT Snoop State
The processor will respond to snoop transactions on the system bus while in the Auto Halt, Stop
Grant or Quick Start state. When a snoop transaction is presented on the system bus the processor
will enter the HALT/GRANT Snoop state. The processor will remain in this state until the snoop
on the system bus has been serviced and the system bus is quiet. After the snoop has been serviced,
the processor will return to the previous Auto Halt, Stop Grant or Quick Start state. If the
HALT/Grant Snoop state is entered from the Quick Start state, then the input signal restrictions of
the Quick Start state still apply in the HALT/Grant Snoop state, except for those signal transitions
that are required to perform the snoop.
4.8.6
Sleep State
The Sleep state is a very low power state in which the processor maintains its context and the
phase-locked loop (PLL) maintains phase lock. The Sleep state can only be entered from the Stop
Grant state. After entering the Stop Grant state, the SLP# signal can be asserted, causing the
processor to enter the Sleep state. The SLP# pin is not recognized in the Normal or Auto Halt
states.
The processor can be reset by the RESET# pin while in the Sleep state. If RESET# is driven active
while the processor is in the Sleep state then SLP# and STPCLK# must immediately be driven
inactive to ensure that the processor correctly executes the Reset sequence.
Input signals (other than RESET#) may not change while the processor is in the Sleep state or
transitioning into or out of the Sleep state. Input signal changes at these times will cause
unpredictable behavior. Thus, the processor is incapable of snooping or latching any events in the
Sleep state. The thermal sensor will respond normally to SMBus transactions when the processor is
in the Sleep state.
While in the Sleep state, the processor is capable of entering its lowest power state, the Deep Sleep
state, by removing the processor’s input clock. PICCLK may be removed in the Sleep state.
4.8.7
Deep Sleep State
The Deep Sleep state is the lowest power mode the processor can enter while maintaining its
context. The Deep Sleep state is entered by stopping the BCLK input to the processor, while it is in
the Sleep or Quick Start state. For proper operation, the BCLK input should be stopped in the low
state.
To re-enter either the Sleep or Quick Start state from the Deep Sleep state, the BCLK input must be
restarted. The processor will return to the Sleep or Quick Start state, as appropriate, after 30 ms.
PICCLK may be removed in the Deep Sleep state. PICCLK should be designed to turn on when
BCLK turns on when transitioning out of the Deep Sleep state.
The input signal restrictions for the Deep Sleep state are the same as for the Sleep state, except that
RESET# assertion will result in unpredictable behavior. The thermal sensor will respond normally
to SMBus transactions when the processor is in the Deep Sleep state.
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