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參數(shù)資料
| 型號： | Pentium II 266 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器) |
| 中文描述： | 32位處理器低功率模塊（帶低能量模塊的32位處理器） |
| 文件頁數(shù)： | 30/50頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | PENTIUM II 266 |
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Pentium
II Processor – Low-Power Module
30
Datasheet
4.6.2
Voltage Regulator Control
The VR_ON pin on the connector allows a digital signal (3.3 V, 5 V safe) to control the voltage
regulator. The system manufacturer can use this signal to turn the module’s voltage regulator on or
off. VR_ON should be controlled as a function of the same digital control signal (SUSB#) used to
control the system’s switched 5 V/3.3 V power planes. The PIIX4E Southbridge defines Suspend B
as the power management state in which power is physically removed from the processor, L2
cache, 443BX Host Bridge/Controller, and voltage regulator. In this state, the SUSB# pin on the
PIIX4E controls these power planes.
Caution:
VR_ON should switch high only when the following conditions are met; V_5(s)
≥
4.5 V, and
V_DC
≥
4.75 V. Turning on VR_ON prior to meeting these conditions will severely damage the
module. See Figure 4 on page 31 for the proper timing sequencing.
4.6.2.1
Voltage Signal Definition and Sequencing
Table 19. Voltage Signal Definitions and Sequences
Signal
Source
Definitions and Sequences
V_DC
System Electronics
DC voltage driven from the power supply and is required
to be between 5V and 21V DC. V_DC powers the
module’s DC-to-DC converter for processor core and I/O
voltages. The module cannot be hot inserted or removed
while V_DC is powered on.
V_3
System Electronics
V_3 is supplied by the system electronics for the 443BX.
V_5
System Electronics
V_5 is supplied by the system electronics for the 443BX’s
5V reference voltage and module’s voltage regulator.
V_3S
System Electronics
V_3S is supplied by the system electronics for the L2
cache devices. Each must be powered off during system
STR and STD states.
VR_ON
System Electronics
Enables the module’s voltage regulator circuit. When
driven active high (3.3V) the voltage regulator circuit on
the module is activated. The signal driving VR_ON
should be a digital signal with a rise/fall time of less than
or equal to 1
μ
s.
V_CORE (also
used as host bus
GTL+ termination
voltage VTT)
Module Only; not on module
interface.
A result of VR_ON being asserted, V_CORE is an output
of the DC-DC regulator on the module and is driven to the
core voltage of the processor. It is also used as the host
bus GTL+ termination voltage, known as VTT.
V_BSB_IO
Module Only; not on module
interface.
V_BSB_IO is 1.8V. The system electronics uses this
voltage to power the L2 cache-to-processor interface
circuitry.
VR_PWRGD
Module
Upon sampling the voltage level of V_CORE for the
processor, minus tolerances for ripple, VR_PWRGD is
driven active high (3.3 V) for the system electronics to
sample prior to providing PWROK to the PIIX4E. If
VR_PWRGD is not sampled active within 1 second of the
assertion of VR_ON the system electronics should
deassert VR_ON.
V_CPUPU
Module
V_CPUPU is 2.5 V. The system electronics uses this
voltage to power the PIIX4E-to-processor interface
circuitry.
V_CLK
Module
V_CLK is 2.5 V. The system electronics uses this voltage
to power the HCLK_(0:1) drivers for the processor clock.
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