Pentium
II Processor – Low-Power Module
16
Datasheet
3.1.7
Clock (9 Signals)
Table 7
lists the module’s clock signals.
G_SUS_STAT1#
I
CMOS
V_3
G_SUS_STAT1#: The SUS_STST1# signal gated by the
Geyserville control logic. G_SUS_STAT1# should be used
in place of the SUS_STAT1# signal in the system
electronics design.
This signal is not implemented on the current module, and
is defined for future upgrade ability purposes only.
G_LO/HI#
I
CMOS
V_3
New signal from a PIIX4E GPIO pin that defines entry into
a Geyserville state change to the Geyserville control logic.
This signal is not implemented on the current module, and
is defined for future upgrade ability purposes only.
G_CPU_STP#
I
CMOS
V_3
The CPU_STP# signal gated by the Geyserville control
logic.
This signal is not implemented on the current module, and
is defined for future upgrade ability purposes only.
VRChgng#
O
CMOS
V_3
A Geyserville control logic signal that indicates that the
actual state change is in progress. The VR setpoint has
changed and the VR is settling. When this signal de-
asserts, the new state is sent to the processor. System
electronics use this signal to generate an SCI to force a
transition out of deep sleep.
This signal is not implemented on the current module, and
is defined for future upgrade ability purposes only.
Table 6. Power Management/Geyserville Signal Descriptions (Sheet 2 of 2)
Name
Type
Voltage
Description
V_3ALWAYS: 3.3 V voltage supply. It is generated whenever V_DC is available and supplied to the
PIIX4E resume well.
Table 7. Clock Signal Descriptions (Sheet 1 of 2)
Name
Type
Voltage
Description
PCLK
I
PCI
V_3S
PCI Clock In:
PCLK is an input to the module is one of the system’s PCI
clocks.
This clock is used by all of the 443BX Host Bridge logic in the
PCI clock domain.
This clock is stopped when the PIIX4E PCI_STP#
signal is asserted and/or during all suspend states.
HCLK[1:0]
I
CMOS
V_CLK
Host Clock In:
Only HCLK0 is an input to the module from the CK100-M
clock source and is used by the processor and 443BX Host
Bridge/Controller. HCLK0 is the only clock input supplied to the module.
This clock is stopped when the PIIX4E CPU_STP# signal is asserted
and/or during all suspend states.
DCLKO
O
CMOS
V_3
SDRAM Clock Out:
66 MHz SDRAM clock reference generated
internally by the 443BX Host Bridge/Controller onboard PLL. It feeds an
external buffer that produces multiple copies for the SODIMMs.
DCLKRD
I
CMOS
V_3
SDRAM Read Clock:
Feedback reference from the SDRAM clock
buffer. This clock is used by the 443BX Host Bridge/Controller when
reading data from the SDRAM array.
DCLKWR
I
CMOS
V_3
SDRAM Write Clock:
Feedback reference from the SDRAM clock
buffer. This clock is used by the 443BX Host Bridge/Controller when
writing data to the SDRAM array.