參數(shù)資料
型號(hào)： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁(yè)數(shù)： 13/50頁(yè)
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
Datasheet
13
3.1.4
PCI (58 SIGNALS)
Table 4
lists the Pentium II Processor – Low-Power Module’s PCI interface signals.
ST[2:0]
O
AGP
V_3
Status Bus:
Provides information from the arbiter to a AGP Master on
what it may do. These bits only have meaning when GGNT is
asserted.
ADSTB[B:A]
I/O
AGP
V_3
AD Bus Strobes:
Provide timing for double clocked data on the GAD
bus. The agent that is providing data drives these signals. These are
identical copies of each other.
SBSTB
I
AGP
V_3
Sideband Strobe:
Provides timing for a side-band bus. It is always
driven by the agent driving SBA[7:0], i.e., by the AGP master.
Table 3. AGP Signal Descriptions (Sheet 2 of 2)
Name
Type
Voltag
e
Description
Table 4. PCI Signal Descriptions (Sheet 1 of 2)
Name
Type
Voltage
Description
AD[31:0]
I/O
PCI
V_3
Address/Data:
The standard PCI address and data lines. The
address is driven with FRAME# assertion, and data is driven or
received in following clocks.
C/BE[3:0]#
I/O
PCI
V_3
Command/Byte Enable:
The command is driven with FRAME#
assertion, and byte enables corresponding to supplied or
requested data are driven on the following clocks.
FRAME#
I/O
PCI
V_3
Frame:
Assertion indicates the address phase of a PCI transfer.
Negation indicates that one more data transfers are desired by the
cycle initiator.
DEVSEL#
I/O
PCI
V_3
Device Select:
This signal is driven by the 443BX Host
Bridge/Controller when a PCI initiator is attempting to access
DRAM.
DEVSEL# is asserted at medium decode time.
IRDY#
I/O
PCI
V_3
Initiator Ready:
Asserted when the initiator is ready for data
transfer.
TRDY#
I/O
PCI
V_3
Target Ready:
Asserted when the target is ready for a data
transfer.
STOP#
I/O
PCI
V_3
Stop:
Asserted by the target to request the master to stop the
current transaction.
PLOCK#
I/O
PCI
V_3
Lock:
Indicates an exclusive bus operation and may require
multiple transactions to complete. When LOCK# is asserted, non-
exclusive transactions may proceed. The 443BX supports lock for
processor initiated cycles only. PCI initiated locked cycles are not
supported
REQ[4:0]#
I
PCI
V_3
PCI Request:
PCI master requests for PCI.
GNT[4:0]#
O
PCI
V_3
PCI Grant:
Permission is given to the master to use PCI.
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