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參數(shù)資料
| 型號： | Pentium II 266 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器) |
| 中文描述： | 32位處理器低功率模塊（帶低能量模塊的32位處理器） |
| 文件頁數(shù)： | 17/50頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | PENTIUM II 266 |
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Pentium
II Processor – Low-Power Module
Datasheet
17
3.1.8
Voltages (54 Signals)
Table 8
lists the module’s voltage signal definitions.
GCLKIN
I
CMOS
V_3
AGP Clock In:
The GCLKIN input is a feedback reference from the
GCLKO signal.
GCLKO
O
CMOS
V_3
AGP Clock Out:
This signal is generated by the 443BX Host
Bridge/Controller onboard PLL from the HCLK0 host clock reference.
The frequency of GCLKO is 66 MHz. The GCLKO output is used to feed
both the PLL reference input pin on the 443BX Host Bridge/Controller
and the AGP device. The board layout must maintain complete
symmetry on loading and trace geometry to minimize AGP clock skew.
FQS
O
CMOS
V_3S
Frequency Select:
This output signal provides the status of the host
clock frequency to the system electronics.
This signal is static and is
pulled either low or high to the V_CLK voltage supply through a 10-K
resistor. This module is designed for the 66-MHz strapping option shown
below.
FQS=0 indicates 66 MHz
FQS=1 indicates 100 MHz (for future modules)
Table 7. Clock Signal Descriptions (Sheet 2 of 2)
Name
Type
Voltage
Description
Table 8. Voltage Descriptions
Name
Type
Number
Description
V_DC
I
20
DC Input:
5 - 21 V
V_3S
I
9
SUSB# controlled 3.3 V:
Power-managed 3.3 V voltage supply.
An
output of the voltage regulator on the system electronics. This rail is off
during STR, STD, and SOff.
V_5
I
3
SUSC# controlled 5 V:
Power-managed 5 V voltage supply.
An output
of the voltage regulator on the system electronics. This rail is off during
STD and SOff.
V_3
I
16
SUSC# controlled 3.3 V:
Power-managed 3.3 V voltage supply.
An
output of the voltage regulator on the system electronics. This rail is off
during STD and SOff.
VCCAGP
I
4
AGP I/O Voltage:
For this revision of the module, this rail must be
connected to V_3.
V_CPUPU
O
1
Processor I/O Ring:
Driven by the module to power processor interface
signals such as the PIIX4E open-drain pullups for the processor/PIIX4E
sideband signals.
V_CLK
O
1
Processor Clock Rail:
Driven by the module to power the CK100-M
VDDCPU rail.
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