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參數(shù)資料
| 型號(hào)： | Pentium II 266 |
| 廠商： | Intel Corp. |
| 英文描述： | 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器) |
| 中文描述： | 32位處理器低功率模塊（帶低能量模塊的32位處理器） |
| 文件頁數(shù)： | 31/50頁 |
| 文件大?。?/td> | 1003K |
| 代理商： | PENTIUM II 266 |
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Pentium
II Processor – Low-Power Module
Datasheet
31
Figure 4 details the sequencing of Signals and Voltage planes required for normal operation of the
module.
The module provides the VR_PWRGD signal, which indicates that the voltage regulator power is
operating at a stable voltage level. The system manufacturer should use this signal on the system
electronics to control power inputs and to gate PWROK to the PIIX4E Southbridge.
Note:
The VR_ON signal should be driven by a digital signal with a rise/fall time of less than or equal to
1 μs and signaling voltage levels that meet the requirement of Vil(max)=0.4V and Vih(min)=3.0 V.
Figure 4. Power On Sequence Timing
POWER SEQUENCE TIMING
V_DC
1. PWROK on I/O board should be active on when VR_PWRGD is active and V_3S is good.
2. CPU_RST from I/O board should be active for a minimum of 6 ms after PWROK is active and PLL_STP# and CPU_STP# are
inactive. Note that PLL_STP# is an AND condition of RSMRST# and SUSB# on the PIIX4.
3. V_DC >= 4.7V, V_5>=4.5V, V_3S>=3.0V.
4. V_CPUPU and V_CLK are generated on the Intel Mobile Module.
5. This is the 5V power supplied to thep rocessor module connector. This should be the first 5V plane to power up.
V_3
V_5
VR_PWRGD
V_3S
VR_ON
0 MS MIN
0 MS MIN
0 MS MIN
6 MS MAX
NOTE 3
V_CPUPU/
V_CLK
SEE NOTE 5
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