參數(shù)資料
型號(hào)： Pentium II 266
廠商： Intel Corp.
英文描述： 32-Bit Processor With Low-Power Module(帶低能量模塊的32位處理器)
中文描述： 32位處理器低功率模塊（帶低能量模塊的32位處理器）
文件頁(yè)數(shù)： 39/50頁(yè)
文件大?。?/td> 1003K
代理商： PENTIUM II 266
Pentium
II Processor – Low-Power Module
Datasheet
39
4.8.2
Normal State
The Normal state of the processor is the normal operating mode where the processor’s internal
clock is running and the processor is actively executing instructions.
4.8.3
Auto Halt State
This is a low power mode entered by the processor through the execution of the HLT instruction.
The power level of this mode is similar to the Stop Grant state. A transition to the Normal state is
made by a halt break event (one of the following signals going active: NMI, INTR, BINIT#, INIT#,
RESET#, FLUSH# or SMI#).
Asserting the STPCLK# signal while in the Auto Halt state causes the processor to transition to the
Stop Grant or Quick Start state, where a Stop Grant Acknowledge bus cycle is issued. By
deasserting STPCLK#, system logic can return the processor to the Auto Halt state without issuing
a new Halt bus cycle.
The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management
Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the
Intel
Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide,
for more
information. No Halt bus cycle is issued when returning to the Auto Halt state from SMM.
The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have
been flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle.
Transitions in the A20M# pin are recognized while in the Auto Halt state.
Table 23. Processor Clock State Characteristics
Clock State
Exit Latency
Power
Snooping
System Uses
Normal
N/A
Varies
Yes
Normal program
execution
Auto Halt
Approximately 10 bus clocks
1.2 W
Yes
S/W controlled entry idle
mode
Stop Grant
10 bus clocks
1.2 W
Yes
H/W controlled entry/exit
throttling
Quick Start
Through snoop
, to HALT/Grant
Snoop state: immediate
Through STPCLK#
, to Normal
state: 10 bus clocks
0.5 W
Yes
H/W controlled entry/exit
throttling
HALT/
Grant Snoop
A few bus clocks after the end of
snoop activity.
Not
specified
Yes
Supports snooping in the
low power states
Sleep
To
Stop Grant
state
10 bus clocks
0.5 W
No
H/W controlled entry/exit
desktop idle mode
support
Deep Sleep
30
μs
100 mW
No
H/W controlled entry/exit
powered-on suspend
support
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