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CHAPTER 17 STANDBY FUNCTION
User
’
s Manual U15017EJ2V0UD
17.3 HALT Mode
17.3.1 HALT mode setting and operating states
The HALT mode is selected by setting (to 1) the HLT bit of the standby control register (STBC).
The only writes that can be performed on STBC are 8-bit data writes by means of a dedicated instruction. HALT
mode setting is therefore performed by means of the
“
MOV STBC, #byte
”
instruction.
If interrupts are enabled (when the IE bit of the program status word (PSW) is set to 1, write a NOP instruction
three times after the instruction that sets the HALT mode (after releasing the HALT mode). Otherwise, two or more
instructions may be executed before an interrupt is acknowledged (after releasing the HALT mode). As a result, the
execution sequence of the interrupt processing and instructions may be changed. To prevent troubles due to changes
in the execution sequence, the above processing is necessary.
Caution If HALT mode setting is performed when a condition that releases HALT mode is in effect, HALT
mode is not entered, and execution of the next instruction, or a branch to a vectored interrupt
service program, is performed. To ensure that a definite HALT mode setting is made, interrupt
requests should be cleared, etc. before entering HALT mode.
Table 17-1. Operating States in HALT Mode
Clock oscillator
Operating
Internal system clock
Operating
CPU
Operation stopped
Note
I/O lines
Retain state prior to HALT mode setting
Peripheral functions
Continue operating
Internal RAM
Retained
Note
Macro service processing is executed.
17.3.2 HALT mode release
HALT mode can be released by the following two sources.
Maskable interrupt request (vectored interrupt/context switching/macro service)
RESET input
Release sources and an outline of operations after release are shown in Table 17-2. Figure 17-4 shows operations
after HALT mode release.