![](http://datasheet.mmic.net.cn/390000/PD784976A_datasheet_16826985/PD784976A_103.png)
103
CHAPTER 5 CLOCK GENERATOR
User
’
s Manual U15017EJ2V0UD
Figure 5-2. Format of Standby Control Register (STBC)
Note
A CPU clock can also be selected using the oscillation mode select register (CC).
Cautions
1. If the STOP mode is used when using external clock input, the EXTC bit of the oscillation
stabilization time specification register (OSTS) must be set (to 1) before setting the STOP
mode. If the STOP mode is used with the EXTC bit of the OSTS cleared (to 0) when using
external clock input, the
μ
PD784975A may suffer damage or reduced reliability.
When setting the EXTC bit of the OSTS to 1, be sure to input a clock in phase reverse
to that of the clock input to the X1 pin, to the X2 pin (refer to 4.3.1).
2. Execute an NOP instruction three times after the standby instruction (after the standby
mode has been released). Otherwise, the standby instruction cannot be executed if
execution of the standby instruction and an interrupt request contend, and the interrupt
is acknowledged after two or more instructions following the standby instruction have
been executed. The instruction that is executed before acknowledging the interrupt is
the one that is executed within up to 6 clocks after the standby instruction has been
executed.
Example
MOV STBC #byte
NOP
NOP
NOP
Remark
f
XX
:
f
X
:
Main system frequency (f
X
or f
X
/2)
Main system clock oscillation frequency
0
0
CK1
CK0
0
0
STP
HLT
7
6
5
4
3
2
1
0
Symbol
STBC
Address: 0FFC0H After reset: 30H R/W
0
0
1
1
STP
0
0
1
1
0
1
0
1
HLT
0
1
0
1
CPU clock selection
Note
(in through-rate clock mode or oscillation division mode)
Operation specification flag
f
XX
(f
X
, f
X
/2)
f
XX
/2
(f
X
/2, f
X
/2
2
)
f
XX
/2
2
(f
X
/2
2
, f
X
/2
3
)
f
XX
/2
3
(f
X
/2
3
, f
X
/2
4
)
Normal operation mode
HALT mode (cleared automatically when HALT mode is released)
STOP mode (cleared automatically when STOP mode is released)
IDLE mode (cleared automatically when IDLE mode is released)
CK0
CK1