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CHAPTER 9 WATCHDOG TIMER
User
’
s Manual U15017EJ2V0UD
9.2 Control Register
Watchdog timer mode register (WDM)
WDM is the 8-bit register that controls watchdog timer operation.
To prevent the watchdog timer from erroneously clearing this register due to a runaway program, this register is
only written by a special instruction. This special instruction has a special code format (4 bytes) in MOV WDM,
#byte instruction. Writing takes place only when the third and fourth op codes are mutual 1
’
s complements. If
the third and fourth op codes are not mutual 1
’
s complements and not written, the operand error interrupt is
generated. In this case, the return address saved in the stack is the address of the instruction that caused the
error. Therefore, the address that caused the error can be identified from the return address saved in the stack.
If returning by simply using the RETB instruction from the operand error, an infinite loop results.
Since an operand error interrupt is generated only when the program is running wild (the correct special instruction
is only generated when MOV WDM, #byte is described in the RA78K4 NEC assembler), make the program initialize
the system.
Other write instructions (MOV WDM, A; AND WDM, #byte; SET1 WDM7, etc.) are ignored and nothing happens.
In other words, WDM is not written and interrupts such as operand error interrupts are not generated.
After a system reset (RESET input), when the watchdog timer starts (when the RUN bit is set to 1), WDM contents
cannot change. Only a reset can stop the watchdog timer. The watchdog timer can be cleared by a special
instruction.
WDM can be read by 8-bit data transfer instructions.
RESET input sets WDM to 00H.
Figure 9-2 shows the format of WDM.