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CHAPTER 16 INTERRUPT FUNCTION
User’s Manual U15017EJ2V0UD
16.3 Interrupt Servicing Control Registers
μ
PD784975A interrupt servicing is controlled for each interrupt request by various control registers that perform
interrupt servicing specification. The interrupt control registers are listed in Table 16-3.
Table 16-3. Control Registers
Register Name
Symbol
Function
Interrupt control registers
WDTIC, PIC0, PIC1, PIC2,
CSIIC0, CSIIC1, TMIC00,
TMC01, KSIC, TMIC50,
TMIC51, ADIC, REMIC,
CSIIC2, SERIC0, SRIC0,
STIC0, WTIIC, WTIC
Record generation of interrupt request, control
masking, specify vectored interrupt servicing or macro
service processing, enable or disable context switching
function, and specify priority.
Interrupt mask register
MK0 (MK0L, MK0H), MK1L
Controls masking of maskable interrupt request.
Associated with mask control flag in interrupt control
register. MK0 can be accessed in word or byte units.
MK1L can be accessed in byte units.
In-service priority register
ISPR
Records priority of interrupt request currently accepted.
Interrupt mode control register
IMC
Controls nesting of maskable interrupt with priority
specified to lowest level (level 3).
Interrupt select control register
SNMI
Selects whether to use interrupt signal from watchdog
timer as maskable or non-maskable interrupt.
Watchdog timer mode register
WDM
Controls operation of watchdog timer.
An interrupt control register is allocated to each interrupt source. The flags of each register perform control of the
contents corresponding to the relevant bit position in the register. The interrupt control register flag names
corresponding to each interrupt request signal are shown in Table 16-4.