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102
CHAPTER 5 CLOCK GENERATOR
User
’
s Manual U15017EJ2V0UD
5.3 Control Register
(1) Standby control register (STBC)
This register is used to set the standby mode and select internal system clock. For the details of the standby
mode, refer to
CHAPTER 17 STANDBY FUNCTION
.
The write operation can be performed only using the dedicated instruction to avoid entering into the standby
mode due to an inadvertent program loop. The dedicated instruction, MOV STBC, #byte, have a special code
structure (4 bytes). The write operation is performed only when the OP code of the 3rd byte and 4th byte are
mutual 1
’
s complements. When the 3rd byte and 4th byte are not mutual 1
’
s complements, the write operation
is not performed and an operand error interrupt is generated. In this case, the return address saved in the stack
area indicates the address of the instruction that caused an error. Therefore, the address that caused an error
can be determined from the return address that is saved in the stack area.
If a return from an operand error is performed simply with the RETB instruction, an infinite loop will be caused.
Because the operand error interrupt occurs only in the case of an inadvertent program loop (if MOV STBC,
#byte is described, only the correct dedicated instruction is generated in NEC
’
s RA78K4 assembler), initialize
the system for the program that processes an operand error interrupt.
Other write instructions such as MOV STBC, A; AND STBC, #byte; and SET1 STBC.7 are ignored and no
operation is performed. In other words, neither is a write operation to STBC performed nor is an interrupt such
as an operand error interrupt generated. STBC can be read out any time by means of a data transfer instruction.
RESET input sets STBC to 30H.
Figure 5-2 shows the format of STBC.
The standby control register (STBC) is used to select a CPU clock, a frequency division ratio, and a mode
(normal operation, HALT, IDLE, or STOP).
STBC is set using an 8-bit memory manipulation instruction.
RESET input sets STBC to 30H.