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179
CHAPTER 11 A/D CONVERTER
User
’
s Manual U15017EJ2V0UD
11.4 Operation of A/D Converter
11.4.1 Basic operation of A/D converter
(1) Select one channel for A/D conversion by using the A/D converter input select register (ADIS).
(2) The sample & hold circuit samples the voltage input to the selected analog input channel.
(3) The sample & hold circuit enters the hold status after it has performed sampling for fixed time, and holds the
input analog voltage until the A/D conversion is completed.
(4) Bit 7 of the successive approximation register (SAR) is set. The tap selector sets the voltage tap of the series
resistor string to (1/2) AV
DD
.
(5) The voltage comparator compares the voltage difference between the voltage of the series resistor string and
voltage tap. If the input analog voltage is greater than (1/2) AV
DD
, the MSB of the SAR remains set. If it is
less than (1/2) AV
DD
, MSB is reset.
(6) Bit 6 of the SAR is automatically set, and the next comparison is performed. The voltage tap of the series
resistor string is selected as follows, depending on the value of bit 7 to which the result has been already set.
Bit 7 = 1: (3/4) AV
DD
Bit 7 = 0: (1/4) AV
DD
This voltage tap is compared with the input analog voltage. Depending on this result, bit 6 of the SAR is
manipulated as follows:
If input analog voltage
≥
voltage tap: Bit 6 = 1
If input analog voltage
≤
voltage tap: Bit 6 = 0
(7) Comparison continues like this up to bit 0 of the SAR.
(8) When comparison of 8 bits has been completed, the valid digital result remains in the SAR, and its value is
transferred and latched to the A/D conversion result register (ADCR).
At the same time, an A/D conversion end interrupt request (INTAD) is generated.
Caution The first A/D conversion result obtained immediately after setting bit 7 (ADCS) of the A/D
converter mode register (ADM) to 1 is undefined and should be discarded by polling the A/D
conversion end interrupt request (INTAD).