
10
User’s Manual U15017EJ2V0UD
CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
GENERAL........................................................................................................................23
Features ................................................................................................................................25
Application Fields ...............................................................................................................25
Ordering Information ..........................................................................................................25
Pin Configuration (Top View).............................................................................................26
Block Diagram .....................................................................................................................28
Functional Outline...............................................................................................................29
Mask Option .........................................................................................................................31
CHAPTER 2
2.1
2.2
PIN FUNCTIONS .............................................................................................................32
Pin Function List .................................................................................................................32
Pin Functions.......................................................................................................................36
2.2.1
P00 to P03 (Port 0) ................................................................................................................. 36
2.2.2
P10 to P17 (Port 1) ................................................................................................................. 36
2.2.3
P20, P25 to P27 (Port 2)......................................................................................................... 36
2.2.4
P40 to P47 (Port 4) ................................................................................................................. 37
2.2.5
P50 to P57 (Port 5) ................................................................................................................. 37
2.2.6
P60 to P67 (Port 6) ................................................................................................................. 37
2.2.7
P70 to P77 (Port 7) ................................................................................................................. 38
2.2.8
P80 to P87 (Port 8) ................................................................................................................. 38
2.2.9
P90 to P97 (Port 9) ................................................................................................................. 38
2.2.10
P100 to P107 (Port 10) ........................................................................................................... 39
2.2.11
FIP0 to FIP15 .......................................................................................................................... 39
2.2.12
V
LOAD
........................................................................................................................................ 39
2.2.13
AV
DD
......................................................................................................................................... 39
2.2.14
AV
SS
.......................................................................................................................................... 39
2.2.15
RESET ..................................................................................................................................... 39
2.2.16
X1 and X2 ................................................................................................................................ 39
2.2.17
V
DD0
to V
DD2
............................................................................................................................. 39
2.2.18
V
SS0
and V
SS1
........................................................................................................................... 39
2.2.19
V
PP
(
μ
PD78F4976A only) ........................................................................................................ 39
2.2.20
IC (Mask ROM product only) .................................................................................................. 40
Pin I/O Circuits and Connections of Unused Pins .........................................................41
2.3
CHAPTER 3
3.1
3.2
3.3
CPU ARCHITECTURE ....................................................................................................44
Memory Space .....................................................................................................................44
Internal ROM Area ...............................................................................................................48
Base Area .............................................................................................................................49
3.3.1
Vector table area ..................................................................................................................... 50
3.3.2
CALLT instruction table area................................................................................................... 50
3.3.3
CALLF instruction entry area .................................................................................................. 51
Internal Data Area................................................................................................................52
3.4.1
Internal RAM area ................................................................................................................... 52
3.4.2
Special function register (SFR) area ...................................................................................... 54
μ
PD78F4976A Memory Mapping........................................................................................55
3.4
3.5