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CHAPTER 13 ASYNCHRONOUS SERIAL INTERFACE
User’s Manual U15017EJ2V0UD
(2) Asynchronous serial interface status register 0 (ASIS0)
ASIS0 is a register used to display the type of error when a receive error occurs.
ASIS0 can be read by a 1-bit or 8-bit memory manipulation instructions.
RESET input sets ASIS0 to 00H.
Figure 13-3. Format of Asynchronous Serial Interface Status Register 0 (ASIS0)
Address: 0FF72H After reset: 00H R
Symbol
7
6
5
4
3
<2>
<1>
<0>
ASIS0
0
0
0
0
0
PE0
Note 1
FE0
Note 2
OVE0
Note 3
PE0
Parity error flag
0
Parity error not generated
1
Parity error generated
(when data is read from the receive buffer, or when a 1-byte data is received)
FE0
Framing error flag
0
Framing error not generated
1
Framing error generated
Note 4
(when stop bit(s) is not detected)
OVE0
Overrun error flag
0
Overrun error not generated
(when the next receive operation is completed before the CPU reads the
receive data from RXB0)
1
Overrun error generated
Note 5
(when data is read from receive buffer register)
Notes 1.
The parity error flag is cleared if the subsequent parity bit detection is correctly performed.
2.
Only the first stop bit in the receive data is detected, regardless of the number of stop bits.
3.
The contents of receive shift register 0 (RX0) are transferred to receive buffer register 0 (RXB0)
each time one character is received. When an overrun error occurs, the subsequent receive data
is overwritten to RXB0. Consequently, the data read from RXB0 is the one received after the
overwritten data.
4.
Even if the stop bit length has been set to 2 bits with bit 2 (SL0) of the asynchronous serial interface
mode register 0 (ASIM0), stop bit detection during reception is only 1 bit.
5.
Be sure to read RXB0 when an overrun error occurs.
An overrun error is generated each time data is received until RXB0 is read.
Caution
Be sure to set bits 3 to 7 of ASIS0 to 0.