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26
User
’
s Manual U15017EJ2V0UD
CHAPTER 1 GENERAL
1.4 Pin Configuration (Top View)
100-pin plastic QFP (14
×
20):
μ
PD784975AGF-
×××
-3BA, 78F4976AGF-3BA
Cautions 1. Directly connect the IC (Internally Connected) pin to V
SS1
in the normal operation mode.
2. When the A/D converter is used (ADCS = 1), use the AV
DD
pin with the same potential as V
DD1
.
When the A/D converter is not used (ADCS = 0), the AV
DD
pin can be used with the same
potential as V
SS1
.
3. Connect the AV
SS
pin to V
SS1
.
Remarks 1.
When the
μ
PD784976A Subseries is used in applications where the noise generated inside the
microcontroller needs to be reduced, the implementation of noise reduction measures, such as
supplying voltage to V
DD0
and V
DD1
individually and connecting V
SS0
and V
SS1
to different ground
lines, is recommended. Always keep V
DD0
at the same potential as the V
DD1
. In addition, always
keep V
SS0
at the same potential as V
SS1
.
2.
The value in parentheses is valid for the
μ
PD78F4976A.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
AV
DD
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
P00/ANI8
P01/ANI9
P02/ANI10
P03/ANI11
AV
SS
V
SS1
X1
X2
V
DD1
P20/TI00
P25/SI0/R
X
D0
P26/SO0/T
X
D0
P27/SCK0/ASCK0
P67/INTP2
P66/TIO51
P65/INTP1
P64/INTP0
P63/TIO50
P62/SCK1
P61/SO1
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
F
P
P
P
P
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
V
LOAD
V
DD2
P74/FIP20
P75/FIP21
P76/FIP22
P77/FIP23
P80/FIP24
P81/FIP25
P82/FIP26
P83/FIP27
P84/FIP28
P85/FIP29
P86/FIP30
P87/FIP31
P90/FIP32
P91/FIP33
P92/FIP34
P93/FIP35
P94/FIP36
P95/FIP37
P96/FIP38
P97/FIP39
P100/FIP40
P101/FIP41
P102/FIP42
P103/FIP43
P104/FIP44
P105/FIP45
P106/FIP46
P107/FIP47
10099989796959493929190898887868584838281
P
P
P
P
P
P
P
P
P
V
S
V
D
R
P
P
P
P
P
P
P
P
3132333435363738394041424344454647484950
IC (V
PP
)