參數(shù)資料
型號： P95020NQG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 94/169頁
文件大小： 4297K
代理商： P95020NQG
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
30
2011 Integrated Device Technology, Inc.
Class D – ID HI and LO Registers
This 24 bit read-only register contains a unique ID for each block.
ID_HI: IC Address = Page-2: 16(0x10), C Address = 0xA210
ID_LO: IC Address = Page-2: 17(0x11), C Address = 0xA211
Table 18. Class D – ID HI and LO Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
DESCRIPTION / COMMENTS
[15:0] ID
4D52h
R
Unique identifier.
Class D – VERSION HI and LO Registers
This 24 bit read-only register contains a unique version identifier for each block.
VERSION_HI: IC Address = Page-2: 18(0x12), C Address = 0xA212
VERSION_LO: IC Address = Page-2: 19(0x13), C Address = 0xA213
Table 19. Class D – VERSION HI and LO Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
DESCRIPTION / COMMENTS
[15:0] VERSION
0110h
R
Bits[15:8] updated on major RTL code change.
Bits[7:4] updated on minor RTL code change.
Bits[3:0] updated on metal layer bug fix.
Class D – STATUS Registers
These are read-only status registers which provide feedback on the operation of the DSP Filtering functions.
STATUS0: IC Address = Page-2: 20(0x14), C Address = 0xA214
Table 20. Class D – STATUS0 Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
DESCRIPTION / COMMENTS
[3:0]
fs_clk_synced_loss_cnt0
0h
R
Count of the number of times synchronization to
i_den is lost since last initialize.
[6:4]
den_jitter
000b
R
latched max value of i_den jitter detected after
fs_clk_synced. Cleared on initialize. How many
fclks is i_den for ch0 jittering between samples.
7
fs_clk_synced
0b
R
1 = Input sample rate (i_den for ch0) is properly
locked to fclk (within tolerance).
STATUS1: IC Address = Page-2: 21(0x15), C Address = 0xA215
Table 21. Class D – STATUS1 Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
DESCRIPTION / COMMENTS
[7:0] fclks_per_ch0_in_sample
00h
R
Multiply this value by 32 to get the number of fclks between each ch0
input data sample. Knowing the fclk frequency you can then determine
sample rate. Also useful in making sure there are enough fclks to allow
the DSP filtering processes to complete before the next input sample.
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參數(shù)描述
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