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參數(shù)資料
| 型號： | P95020NQG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | 10 X 10 MM, 0.85 MM HEIGHT, QFN-132 |
| 文件頁數(shù)： | 154/169頁 |
| 文件大?。?/td> | 4297K |
| 代理商： | P95020NQG |
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IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
85
2011 Integrated Device Technology, Inc.
GENERAL PURPOSE TIMERS
GP Timers – General Description
The IDTP95020 includes two independent general
purpose timers. The first is an 8-bit General Purpose
Timer that operates on a user-selectable time base of
32.768 kHz, 1024 Hz, 1Hz, or 1 Minute. The second is an
8-bit Watchdog Timer that operates on a user-selectable
time base of 8Hz, 1Hz, 0.5Hz, or 1 Minute
General Purpose Timer
To use the General Purpose Timer (GP), an 8-bit value
must be loaded in to the General Purpose Timer Count
Register and a time base (count interval) value must also
be loaded into bits [1:0] of the General Purpose Timer
Timebase Register. The General Purpose Timer can then
be enabled by writing a logic ‘1’ into bit 0 (GPT_EN) of the
General Purpose Timer Enable Register. The General
Purpose Timer will then begin counting and continue until
the count value is equal to the value specified in the
General Purpose Timer Count Register (timeout value).
When the timeout value is reached, the GPTIMEOUT bit is
set to a logic ‘1’ in the Timer Interrupt Status Register. If
the General Purpose Timer Interrupt has been enabled by
setting bit 0 in the Timer Interrupt Register to a logic ‘1’
then an interrupt is generated to alert the system that the
timeout value has been reached. THE GPTIMEOUT bit is
cleared by writing a logic ‘1’ to the GPTIMEOUT bit in the
Timer Interrupt Status Register. Following the interrupt,
the General Purpose Timer will stop and reset to 0. Bit 0
of the General Purpose Timer Enable Register is also
reset to 0 following the interrupt. However, the content of
General Purpose Timer Count Register and the General
Purpose Timer Timebase Value Registers are maintained
and the count cycle can be repeated by writing a logic ‘1’
to GPT_EN.
When the General Purpose Timer is
counting, writing a logic ‘0’ to GPT_EN will reset and stop
the timer.
Watchdog Timer
To use the Watchdog Timer (WD), an 8-bit value must be
loaded in to the Watchdog Timer Count Register and a
time base (count interval) value must also be loaded into
bits [5:4] of the General Purpose Timer Timebase Register.
The Watchdog Timer can then be enabled by writing a
logic ‘1’ into bit 0 (WDT_EN) of the Watchdog Timer
Enable Register. The Watchdog Timer will then begin
counting and continue until the count value is equal to the
value specified in the Watchdog Timer Count Register
(timeout value). When the timeout value is reached, the
WDTIMEOUT bit is set to a logic ‘1’ in the Timer Interrupt
Status Register. If the Watchdog Timer Interrupt has been
enabled by setting bit 4 in the Timer Interrupt Register to a
logic ‘1’ then an interrupt is generated to alert the system
that the timeout value has been reached.
THE
WDTIMEOUT bit is cleared by writing a logic ‘1’ to the
WDTIMEOUT bit in the Timer Interrupt Status Register.
Following the interrupt, the Watchdog Timer will stop and
reset to 0. Bit 0 of the Watchdog Timer Enable Register is
also reset to 0 following the interrupt. The Watchdog
Timer can be reset anytime during the count interval by
writing a logic ‘1’ to bit 4 of the Watchdog Timer Enable
Register before the timer times out to prevent an interrupt
from being generated. After reset, the Watchdog Timer
automatically restarts.
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| P95020NQG8 | 制造商:Integrated Device Technology Inc 功能描述:Power Management and Control 132-Pin QFN EP T/R 制造商:Integrated Device Technology Inc 功能描述:POWER MANAGEMENT AUDIO & CONTROL - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:Integrates Audio, LED B/Light Pwr Mgt |
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