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參數(shù)資料
| 型號： | P95020NQG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | 10 X 10 MM, 0.85 MM HEIGHT, QFN-132 |
| 文件頁數(shù)： | 142/169頁 |
| 文件大?。?/td> | 4297K |
| 代理商： | P95020NQG |
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IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
74
2011 Integrated Device Technology, Inc.
Clock Generator – PLL Control
The PLL in the CKGEN module is powered on/off by setting bits [2:0] in the CKGEN_PLL_CFG register as shown below.
Table 110. Clock Generator PLL Control Register 0xA034[2:0]
S2 S1 S0 PLL BEHAVIOR
0
PLL OFF
0
1
PLL power up with 26MHz TCXO_IN as reference clock
0
1
0
PLL power up with 32kHz XTAL_IN as reference clock
0
1
PLL power up with 26MHz TCXO_IN as reference clock
1
0
PLL OFF
1
0
1
PLL power up with 12MHz TCXO_IN as reference clock
1
0
PLL power up with 13MHz TCXO_IN as reference clock
1
PLL power up with 19.2MHz TCXO_IN as reference clock
The 12 MHz and 48 MHz outputs are enabled/disabled by setting bits 0xA034[7:6] in the CKGEN_PLL_CFG register. One or
both of the clock outputs will be enabled when a “1” is written into the corresponding register location for the output in question.
Clock Generator – Oscillator Circuit
The CKGEN module may use an external 32.768 kHz crystal connected to the XTALIN pin. The oscillator circuit does not
require any external resistors or capacitors to operate.
Table 111 specifies several crystal parameters for the external crystal. The typical startup time is less than one second when
using a crystal with the specified characteristics.
Table 111. Clock Generator Crystal Specifications
SYMBOL PARAMETER
MIN
TYP
MAX
UNITS
fo
Nominal Frequency
32.768
kHz
ESR
Series Resistance
80
k
Ω
CL
Load Capacitance
12
pF
Clock Generator – Power Source
The CKGEN module receives its power from an on-chip
LDO.
The CKGEN power is controlled via the
“PSTATE_ON” bit in the Power State and Switch Control
Register 0xA031[4] (see Table 225 on Page 136). Setting
that register is automatic whenever there is a pending
interrupt targeting the embedded processor.
The
“PSTATE_ON” bit can be cleared by writing a logic “1” if
there is a software command to power down the CKGEN.
Please be aware that powering down the CKGEN should
be the last operation by the software, since once CKGEN
is powered down, there will be no clock for the internal
register access bus or IC bus. The IDTP95020 has a
minor delay when the PSTATE_ON bit is cleared to allow
the access to be finished.
When CKGEN is powered, the CLK8M clock will be
available so the IC/processor will be active. The chip’s
registers can be accessed. However, the PLLs will not be
on. To turn on the PLLs, the S2:S0 registers need to be
set (see Table 112)
.
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