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參數(shù)資料
| 型號： | P95020NQG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | 10 X 10 MM, 0.85 MM HEIGHT, QFN-132 |
| 文件頁數(shù)： | 35/169頁 |
| 文件大小： | 4297K |
| 代理商： | P95020NQG |
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IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
13
2011 Integrated Device Technology, Inc.
MODULE
PIN#
PIN NAME
DESCRIPTION
I/O TYPE
HOTSWAP
B47
HSCTRL1
Hot Swap Control Input 1
D-I
A58
HSO1
Hot Swap Output 1
A-O
B48
HSPWR
Hot Swap Switches Power Input
AP-I
A59
HSO2
Hot Swap Output 2
A-O
B49
HSCTRL2
Hot Swap Control Input 2
D-I
CHARGER
A60
CHRG_GND1
Pins A60 and B50 are the Power GND Pins for the Switching Regulator
in the Charger. Due to their higher current requirement they are
internally tied together and must be connected externally at the PC board
also.
A-I
B50
CHRG_GND2
A-I
A61
CHRG_SW1
Pins A61 and B51connect to the inductor of the switch-mode step-down
regulator for the Battery Charger. Due to their higher current
requirement they are internally tied together and must be connected
externally at the PC board also.
A-O
B51
CHRG_SW2
A-O
A62
CHRG_INPUT1
Pins A62 and B52 provide 5V VBUS Input Power from the USB or from an
external AC adaptor supply. Due to the pins higher current requirement,
they are internally tied together and must be connected externally at the
PC board also.
AP-I
B52
CHRG_INPUT2
AP-I
A63
CHRG_SYSVCC1
Pins A63 and B53 are System VCC Output (VSYS). Due to their higher
current requirement they are internally tied together and must be
connected externally at the PC board also.
A-O
B53
CHRG_SYSVCC2
A-O
A64
CHRG_BAT1
Pins A64 and B64 form the positive battery lead connection to a single cell
Li-Ion/Li-Poly battery. Due to their higher current requirement they are
internally tied together and must be connected externally at the PC board
also.
AP-I/O
B54
CHRG_BAT2
AP-I/O
A65
CHRG_CLSEN
Input Current Limit Sense/filtering pin for current limit detection
A-I
B55
CHRG_ICHRG
Current setting. Connect to a current sense resistor
AP-I/O
A66
CHRG_GATE
Gate Drive for (Optional) External Ideal Diode
A-O
B56
CHRG_NTC
Thermal Sense, Connect to a battery’s thermistor
A-I
A67
CHRG_VNTC
NTC Power output. This pin provides power to the NTC resistor string.
AP-O
This output is automatically CHRG_SYSVCC level but only enabled
when NTC measurement is necessary to save power.
B57
GND_BAT/ADCGND
GND_BAT and ADCGND: Shared analog ground pin for battery charger
and ADC.
GND
GPIO_TSC
A68
DGND
Digital Ground
GND
B58
POR_OUT
Power-On-Reset Output, Active Low
GPIO-OUT
A69
SW_DET
Switch Detect Input
GPIO
B59
GPIO1/SW_OUT/
PENDOWN
GPIO 1: General Purpose I/O # 1
GPIO
SW_OUT: Switch Detect Output
PENDOWN: PENDOWN Detect Output
A70
GPIO3/LED2
GPIO 3: General Purpose I/O # 3
GPIO
LED2: Charger LED # 2 Indicates charging complete
B60
GPIO2/LED1
GPIO 2: General Purpose I/O # 2
GPIO
LED1: Charger LED # 1 Indicates charging in progress
A71
NC
No Connect
NC
A72
GPIO4/CHRG_ILIM
GPIO 4: General Purpose I/O # 4
CHRG_ILIM: Control the limit of the Charger Pre-Regulator.
CHRG_ILIM = 0, limit current to 500mA; CHRG_ILIM = 1, limit current to
1.5A.
GPIO
Thermal
EP
Exposed Paddle
Exposed paddle (package bottom). Connect to GND. The exposed
thermal paddle should be connected to board ground plane. The ground
plane should include a large exposed copper pad under the package for
thermal dissipation.
GND
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