參數(shù)資料
型號： P95020NQG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 120/169頁
文件大小： 4297K
代理商： P95020NQG
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
54
2011 Integrated Device Technology, Inc.
I2S2 Port Configuration 1
IC Address = Page-1: 203(0xCB), C Address = 0xA1CB, Offset = 0xCB
Table 85. I2S2 Port Configuration 1 Register
BIT
BIT NAME
DEFAULT SETTING USER TYPE VALUE
DESCRIPTION / COMMENTS
[1:0] BIT_PER_SAMP 00b
RW
00b = 16
01b = 20
10b = 24
11b = RESERVED
[4:2] DIV
000b
RW
0 ~ 7 = div 1 ~ 8
[6:5] MULT
00b
RW
00b = x1 or less
01b = x2
10b = RESERVED
11B = RESERVED
7
BASE_RATE
0b
RW
0b = 48 kHz
1b = 44.1 kHz
I2S2 Port Configuration 2
IC Address = Page-1: 204(0xCC), C Address = 0xA1CC, Offset = 0xCC
Table 86. I2S2 Port Configuration 2 Register
BIT
BIT NAME DEFAULT SETTING USER TYPE VALUE
DESCRIPTION / COMMENTS
[1:0] FRMT
00b
RW
00b = I2S
01b = Left justified
10b = Right justified
11b = RESERVED
Link format
2
RXEN
0b
RW
0b = Disabled
1b = Port Rx enabled
Rx enable
3
LR_SWAP 0b
RW
0b = Normal operation
1b = L and R swap
Swap left and right at output enable
4
WSINV
0b
RW
0b = Normal Operation
1b = Invert word clock
Invert word clock
5
BCLKINV
0b
RW
0b = Normal Operation
1b = Invert bit clock
Invert bit clock
6
MSS
0b
R
0b = Slave (only)
1b = RESERVED
Slave only
7
TXEN
0b
RW
0b = Disabled
1b = Port Tx enabled
Tx enable
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相關代理商/技術參數(shù)
參數(shù)描述
P95020NQG8 制造商:Integrated Device Technology Inc 功能描述:Power Management and Control 132-Pin QFN EP T/R 制造商:Integrated Device Technology Inc 功能描述:POWER MANAGEMENT AUDIO & CONTROL - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:Integrates Audio, LED B/Light Pwr Mgt
P95020ZDLLG 制造商:Integrated Device Technology Inc 功能描述:124-LGA - Bulk
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P95020ZDNQG 制造商:Integrated Device Technology Inc 功能描述:132-VFQFPN - Bulk
P95020ZDNQG8 制造商:Integrated Device Technology Inc 功能描述:132-VFQFPN - Tape and Reel
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