參數(shù)資料
型號： P95020NQG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù)： 39/169頁
文件大?。?/td> 4297K
代理商： P95020NQG
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
133
2011 Integrated Device Technology, Inc.
When configured as an input, each GPIO can be
configured as level or edge sensitive by setting the
corresponding bit in the GPIO Input Mode Select Register.
When set to level sensitive, the corresponding bit in the
GPIO Data Register will follow the logic level of the GPIO
pin. When set to edge sensitive, the corresponding bit in
the GPIO Data Register will change from a logic ‘0’ to a
logic ‘1’ when the input transitions from low to high (rising
edge or both edges sensitive) or high to low (both edges
sensitive) as determined by the setting in the GPIO Input
Edge Select Register. The value in the GPIO Data
Register will remain a logic ‘1’ until a logic ‘0’ is written into
the register through host or I2C interface. In level sensitive
mode, writing to the GPIO Data Register through host or
I2C will have no effect.
When configured as an input, a GPIO may also generate
an interrupt. Interrupts are always edge sensitive. The
GPIO Input Edge Select Register is used to select which
edge, rising or falling, is used to generate an interrupt.
When an edge is detected, the GPIO Interrupt Status
Register will show a logic ‘1’ in the corresponding bit and
an interrupt will be generated provided the appropriate bit
has been enabled by writing a logic ‘1’ to the GPIO
Interrupt Enable Register. The GPIO Interrupt Status
Register is cleared by writing a logic ‘1’ to the appropriate
bit. Writing a logic ‘0’ will have no effect.
PCON Registers
GPIO Direction Register
IC Address = Page-0: 32(0x20), C Address = 0xA020
IC Address = Page-0: 33(0x21), C Address = 0xA021
Table 216. GPIO Direction Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION / COMMENTS
0
RESERVED 0b
R/W
RESERVED
[10:1]
GPIO_DIR
0000000000b R/W
0 = Input
1 = Output
Each bit sets the corresponding GPIO to either input or output
[15:11] RESERVED
R/W
RESERVED
GPIO Data Register
IC Address = Page-0: 34(0x22), C Address = 0xA022
IC Address = Page-0: 35(0x23), C Address = 0xA023
Table 217. GPIO Data Register
BIT
BIT NAME
DEFAULT
SETTING
SET.
USER
TYPE
DESCRIPTION / COMMENTS
0
RESERVED 0b
R/W
RESERVED
[10:1]
GPIO_DAT
0000000000b
R/W
Pins configured as an output will reflect the value held in the GPIO_DAT register. The
GPIO_DAT register will follow the logic level at the pin for pins configured as level
sensitive inputs. The GPIO_DAT register will change from a 0 to a 1 when the input
transitions state from low to high (rising edge) or high to low (falling edge) as
determined by the GPIO INPUT EDGE SELECT register for pins configured as level
sensitive inputs.
[15:11] RESERVED
R/W
RESERVED
相關PDF資料
PDF描述
P95020NQG8 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
P95020ZNQGI8 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
P95020ZLLG 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
P95020ZLLGI 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA124
P95020ZNQGI 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
相關代理商/技術參數(shù)
參數(shù)描述
P95020NQG8 制造商:Integrated Device Technology Inc 功能描述:Power Management and Control 132-Pin QFN EP T/R 制造商:Integrated Device Technology Inc 功能描述:POWER MANAGEMENT AUDIO & CONTROL - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:Integrates Audio, LED B/Light Pwr Mgt
P95020ZDLLG 制造商:Integrated Device Technology Inc 功能描述:124-LGA - Bulk
P95020ZDLLG8 制造商:Integrated Device Technology Inc 功能描述:124-LGA - Tape and Reel
P95020ZDNQG 制造商:Integrated Device Technology Inc 功能描述:132-VFQFPN - Bulk
P95020ZDNQG8 制造商:Integrated Device Technology Inc 功能描述:132-VFQFPN - Tape and Reel
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*