參數(shù)資料
型號: P95020NQG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 電源管理
英文描述: 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝: 10 X 10 MM, 0.85 MM HEIGHT, QFN-132
文件頁數(shù): 144/169頁
文件大?。?/td> 4297K
代理商: P95020NQG
IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
76
2011 Integrated Device Technology, Inc.
Clock Generator – Clock Accuracy
The accuracy of the clock is dependent upon the accuracy
of the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capacitive
load for which the crystal was trimmed. Additional error is
added by crystal frequency drift caused by temperature
shifts. External circuit noise coupled into the 32 KHz
oscillator circuit may result in the output clock wandering
when 32 KHz is set to be the reference input of the PLL.
The PC board layout must isolate the crystal and oscillator
from noise sources.
Clock Generator - Registers
PLL Configuration Register
IC Address = Page-0: 52(0x34), C Address = 0xA034
Table 114. PLL Configuration Register
BIT
BIT NAME
DEFAULT
SETTING
USER
TYPE
VALUE
DESCRIPTION /
COMMENTS
[2:0] S2/S1/SO
000b
R/W
000b = PLL off
001b = PLL on, 26MHz TCXO_IN as reference clock
010b = PLL on, 32kHz XTAL_IN as reference clock
011b = PLL on, 26MHz TCXO_IN as reference clock
100b = PLL off
101b = PLL on, 12MHz TCXO_IN is reference clock
110b = PLL on, 13 MHz TCXO_IN is reference clock
111b = PLL on, 19.2 MHz TCXO_IN is reference clock
3
RESERVED
0b
R/W
4
SSC_DELTA
0b
R/W
0b = +/- 1%
1b= +/- 2%
SSC frequency offset
setting
5
SSC_EN
0b
R/W
0b = Disabled
1b = Enabled
DCDC 24MHz clock
SSC enable
6
SYS_CLK_OUT_EN 1b
R/W
0b = Disabled
1b = Enabled
SYS_CLK clock output
enabled
7
USB_CLK_OUT_EN 1b
R/W
0b = Disabled
1b = Enabled
USB_CLK clock output
enable
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