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參數(shù)資料
| 型號： | P95020NQG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | 10 X 10 MM, 0.85 MM HEIGHT, QFN-132 |
| 文件頁數(shù)： | 68/169頁 |
| 文件大?。?/td> | 4297K |
| 代理商： | P95020NQG |
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IDTP95020
Product Datasheet
September 2, 2011 Revision 1.3 Final
16
2011 Integrated Device Technology, Inc.
Functional Modes
There are two primary functional modes for operation:
external processor only or simultaneous internal and
external processor operation.
External Processor Control
In this mode of operation, the external processor can
access all internal registers via the IC interface and
receive interrupts via an interrupt pin. The internal
Microcontroller can be powered down or clock gated off.
Combined Internal and External Processor Operation
In this mode of operation, the Microcontroller in the
IDTP95020 will function autonomously or semi-
autonomously based on the content of the on-board or
external ROM. The external Application Processor may or
may not perform additional control functions through the
IC bus interface. Individual time-based or event-based
interrupts generated inside the IDTP95020 device may be
routed internally or externally to be handled separately.
All IC registers can be simultaneously accessed by either
the external Application Processor or the internal
Microcontroller. Access to the I2C registers is arbitrated
via on-chip hardware arbitration.
Register Map
All the IDTP95020 control and status registers accessible
to the Microprocessor are mapped to a 1024 location
address space. This address space maps to:
-
4 x 256 Bytes of IC pages for the IC slave interface
-
1024 consecutive addresses in the embedded
Microprocessor address space
For easy access from the IC slave interface (by default
256 Bytes oriented) the first 16 registers of each page are
global for all the pages.
Each Module is allocated a consecutive address space.
Register address computation:
Address = Base Address + Offset Address
The Base addresses (for both IC and embedded P) are
listed in the following table. The Offset addresses are
defined in different functional Modules.
The offset
address is labeled as “Offset Address” in the Module
Register definition sections.
Table 11 – Register Address Global Mapping
MODULE
SIZE
(BYTES)
BASE ADDRESS
(IC)
BASE
ADDRESS
(6811
μP)
REGISTER
DEFINITION
LOCATION
MODULE DESCRIPTION
Global
Registers
16
Page-x: 000(0x00)
0xA000
Page 146
Global registers are used by the Access
Manager, the first 16 registers of each page are
global for all the pages.
ACCM
16
Page-0: 016(0x10)
0xA010
Page 151
Access manager, including an IC slave and
bus arbiter
PCON
32
Page-0: 032(0x20)
0xA020
Page 133
Power controller, including registers that control
the on/off of the regulators, and control/sense
of the GPIO, power states
Page 76
Clock Generator Registers
RTC
32
Page-0: 064(0x40)
0xA040
Page 79
Real Time Clock
LDO
32
Page-0: 096(0x60)
0xA060
Page 157
Linear regulators, including regulators for
external and internal usage
DC_DC
16
Page-0: 128(0x80)
0xA080
Page 88
Switching regulators and Class-D BTL driver
consisting of three bucks, one 5V boost , one
white LED driver and one Class-D BTL driver
CHARGER
16
Page-0: 144(0x90)
0xA090
Page 62
Battery Charger, including a dedicated
switching buck regulator, an ideal diode, a
precision reference and thermal sensor
GPT
16
Page-0: 160(0xA0)
0xA0A0
Page 86
General purpose timers
RESERVED
16
Page-0: 176(0xB0)
0xA0B0
RESERVED
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