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Figure 57: CAS Write Latency
CK
CK#
Command
DQ
DQS, DQS#
ACTIVE n
BC4
T0
T1
Don’t Care
NOP
T6
T12
NOP
WRITE n
T13
NOP
DI
n + 3
DI
n + 2
DI
n + 1
T14
NOP
DI
n
tRCD (MIN)
NOP
AL = 5
T11
Indicates A Break in
Time Scale
WL = AL + CWL = 11
Transitioning Data
T2
CWL = 6
AUTO SELF REFRESH (ASR)
Mode register MR2[6] is used to disable/enable the ASR function. When ASR is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal 85°C limit (some-
times referred to as 1X refresh rate). In the disabled mode, ASR requires the user to
ensure the DRAM never exceeds a TC of +85°C while in self refresh unless the user ena-
bles the SRT feature listed below when the TC is between +85°C and +95°C.
Enabling ASR assumes the DRAM self refresh rate is changed automatically from 1X to
2X when the case temperature exceeds +85°C. This enables the user to operate the
DRAM beyond the standard 85°C limit up to the optional extended temperature range
of +95°C while in self refresh mode.
The standard self refresh current test specifies test conditions to normal case tempera-
ture (+85°C) only, meaning if ASR is enabled, the standard self refresh current specifica-
SELF REFRESH TEMPERATURE (SRT)
Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled,
the self refresh mode’s refresh rate is assumed to be at the normal +85°C limit (some-
times referred to as 1X refresh rate). In the disabled mode, SRT requires the user to
ensure the DRAM never exceeds a TC of +85°C while in self refresh mode unless the user
enables ASR.
When SRT is enabled, the DRAM self refresh is changed internally from 1X to 2X, regard-
less of the case temperature. This enables the user to operate the DRAM beyond the
standard +85°C limit up to the optional extended temperature range of +95°C while in
self refresh mode. The standard self refresh current test specifies test conditions to nor-
mal case temperature (+85°C) only, meaning if SRT is enabled, the standard self refresh
2Gb: x4, x8, x16 DDR3 SDRAM
Mode Register 2 (MR2)
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
142
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.