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參數(shù)資料
| 型號： | MT41J128M16HA-107:D |
| 元件分類： | DRAM |
| 英文描述： | 128M X 16 DDR DRAM, PBGA96 |
| 封裝： | 9 X 14 MM, LEAD FREE, FBGA-96 |
| 文件頁數(shù)： | 127/210頁 |
| 文件大?。?/td> | 12448K |
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Table 5: 96-Ball FBGA – x16 Ball Descriptions
Symbol
Type
Description
A0, A1, A2, A3, A4,
A5, A6, A7, A8, A9,
A10/AP, A11, A12/
BC#, A13
Input
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one bank (A10
LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). The address inputs also pro-
vide the op-code during a LOAD MODE command. Address inputs are referenced to
VREFCA. A12/BC#: When enabled in the mode register (MR), A12 is sampled during READ
and WRITE commands to determine whether burst chop (on-the-fly) will be performed
(HIGH = BL8 or no burst chop, LOW = BC4). See Table 69 (page 112).
BA[2:0]
Input
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode
register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0]
are referenced to VREFCA.
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All control and address input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
CKE
Input
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is de-
pendent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle),or
active power-down (row active in any bank). CKE is synchronous for
power-down entry and exit and for self refresh entry. CKE is asynchronous for self re-
fresh exit. Input buffers (excluding CK, CK#, CKE, RESET#, and ODT) are disabled during
POWER-DOWN. Input buffers (excluding CKE and RESET#) are disabled during SELF RE-
FRESH. CKE is referenced to VREFCA.
CS#
Input
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the com-
mand decoder. All commands are masked when CS# is registered HIGH. CS#
provides for external rank selection on systems with multiple ranks. CS# is considered
part of the command code. CS# is referenced to VREFCA.
LDM
Input
Input data mask: LDM is a lower-byte, input mask signal for write data. Lower-byte
input data is masked when LDM is sampled HIGH along with the input data during a
write access. Although the LDM ball is input-only, the LDM loading is designed to
match that of the DQ and DQS balls. LDM is referenced to VREFDQ.
ODT
Input
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3 SDRAM. When enabled in normal
operation, ODT is only applied to each of the following balls: DQ[15:0], LDQS, LDQS#,
UDQS, UDQS#, LDM, and UDM for the x16; DQ0[7:0], DQS, DQS#, DM/TDQS, and NF/
TDQS# (when TDQS is enabled) for the x8; DQ[3:0], DQS, DQS#, and DM for the x4. The
ODT input is ignored if disabled via the LOAD MODE command. ODT is referenced to
VREFCA.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command
being entered and are referenced to VREFCA.
RESET#
Input
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input receiv-
er is a CMOS input defined as a rail-to-rail signal with DC HIGH
≥ 0.8 × VDD and DC
LOW
≤ 0.2 × VDDQ. RESET# assertion and desertion are asynchronous.
2Gb: x4, x8, x16 DDR3 SDRAM
Ball Assignments and Descriptions
PDF: 09005aef826aaadc
2Gb_DDR3_SDRAM.pdf – Rev. K 04/10 EN
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
2006 Micron Technology, Inc. All rights reserved.
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