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MC68349 USER'S MANUAL
MOTOROLA
4.4.2 SIM49 Module Configuration
The order of the following SIM49 register initializations is not important; however, time can
be saved by initializing the SYNCR first to quickly increase to the desired processor
operating frequency. The MBAR must be initialized prior to any of the following steps.
Hardware Configuration
D31 and D30 select 8-/16-/32-bit or external termination for CS0 global chip select
D29 configures port A as either address outputs or an input port
Clock Synthesizer Control Register (SYNCR):
Set frequency control bits (W, X, Y, Z) to specify frequency.
Select action taken during loss of crystal (RSTEN bit): activate a system reset or
operate in limp mode.
Select system clock and CLKOUT during LPSTOP (STSIM and STEXT bits).
Module Configuration Register (MCR)
If using the software watchdog, periodic interrupt timer, and/or the bus monitor, select
action taken when FREEZE is asserted (FRZx bits).
Select port B configuration (FIRQ bit). Note that this bit is used in combination with
the bits in the PPARB to program the function of the port B pins.
Select the access privilege for the supervisor/user registers (SUPV bit).
Select the interrupt arbitration level for the SIM49 (IARBx bits).
Autovector Register (AVR)
Select the desired external interrupt levels for internal autovectoring.
System Protection Control Register (SYPCR) (Note that this register can only be written
once after reset.)
Enable the software watchdog, if desired (SWE bit).
If the watchdog is enabled, select whether a system reset or a level 7 interrupt is
desired at timeout (SWRI bit).
If the watchdog is enabled, select the timeout period (SWTx bits).
Enable the double bus fault monitor, if desired (DBFE bit).
Enable the external bus monitor, if desired (BME bit).
Select timeout period for bus monitor (BMTx bits).
Software Watchdog Interrupt Vector Register (SWIV)
If using the software watchdog, program the vector number for a software watchdog
interrupt.