MOTOROLA
MC68349 USER'S MANUAL
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1.4.2 Serial Module
Most digital systems use serial I/O to communicate with host computers, operator
terminals, or remote devices. The MC68349 contains a two-channel, full-duplex universal
synchronous/asynchronous receiver/transmitter (USART). An on-chip baud rate generator
provides standard baud rates up to 76.8k baud independently to each channel's receiver
and transmitter. The module is functionally equivalent to the MC68681/MC2681 DUART.
Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8
bits with even, odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive
buffers and two-byte transmit buffers minimize CPU service calls. A wide variety of error
detection and maskable interrupt capability is provided on each channel. Full-duplex,
autoecho loopback, local loopback, and remote loopback modes can be selected.
Multidrop applications are supported.
A 3.6864-MHz crystal drives the baud rate generators. Each transmit and receive channel
can be programmed for a different baud rate, or an external 1
× and 16× clock input can be
selected. Full modem support is provided with separate request-to-send (RTS) and clear-
to-send (CTS) signals for each channel. Channel A also provides service request signals.
The two serial ports can sustain rates of 3 Mbps with a 25-MHz system clock in 1
× mode,
612 kbps in 16
× mode (6.5 Mbps and 410 kbps @ 16.78 MHz).
1.4.3 System Integration Module
The MC68349 SIM49 provides the external bus interface for both the CPU32+ and the
DMA. It also eliminates much of the glue logic that typically supports the microprocessor
and its interface with the peripheral and memory system. The SIM49 provides
programmable circuits to perform address decoding and chip selects, wait-state insertion,
interrupt handling, clock generation, bus arbitration, watchdog timing, discrete I/O, and
power-on reset timing. A boundary scan test capability is also provided.
1.4.3.1 EXTERNAL BUS INTERFACE. The external bus interface handles the transfer of
information between the internal CPU32+ or DMA controller and memory, peripherals, or
other processing elements in the external address space. Based on the MC68030 bus, the
external bus provides up to 32 address lines and 32 data lines. Address extensions
identify each bus cycle as CPU32+ or DMA initiated, supervisor or user privilege level,
and instruction or data access. The data bus allows dynamic bus sizing for 8-, 16-, or 32-
bit memory devices. Synchronous transfers from the CPU32+ or the DMA can be made in
as little as two clock cycles. Asynchronous transfers allow the memory system to signal
the CPU32+ or DMA when the transfer is complete and to signal the transfer size. An
external master can arbitrate for the bus using a three-wire handshaking interface.
1.4.3.2 SYSTEM CONFIGURATION AND PROTECTION. To achieve maximum system
protection, the MC68349 provides system configuration and various monitors and timers
as part of the SIM49. The SIM49 contains basic power-on reset circuitry as well as a bus
monitor which ensures that the system does not lock up when there is no response to a
memory access. When a catastrophic bus failure occurs, the SIM49 bus