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MC68349 USER’S MANUAL
MOTOROLA
Tracing also affects normal operation of the STOP and LPSTOP instructions. If either
instruction begins execution with T1 set, a trace exception will be taken after the
instruction loads the SR. Upon return from the trace handler routine, execution will
continue with the instruction following STOP (LPSTOP), and the processor will not enter
the stopped condition.
5.6.2.11 INTERRUPTS. There are seven levels of interrupt priority and 192 assignable
interrupt vectors within each exception vector table. Careful use of multiple vector tables
and hardware chaining will permit a virtually unlimited number of peripherals to interrupt
the processor.
Interrupt recognition and subsequent processing are based on internal interrupt request
signals (IRQ7– IRQ1 ) and the current priority set in SR priority mask I2–I0. Interrupt
request level 0 (IRQ7– IRQ1 negated) indicates that no service is requested. When an
interrupt of level 1 through 6 is requested via IRQ6– IRQ1 , the processor compares the
request level with the interrupt mask to determine whether the interrupt should be
processed. Interrupt requests are inhibited for all priority levels less than or equal to the
current priority. Level 7 interrupts are nonmaskable.
IRQ7– IRQ1 are synchronized and debounced by input circuitry on consecutive rising
edges of the processor clock. To be valid, an interrupt request must be held constant for
at least two consecutive clock periods.
Interrupt requests do not force immediate exception processing, but are left pending. A
pending interrupt is detected between instructions or at the end of exception processing—
all interrupt requests must be held asserted until they are acknowledged by the CPU. If
the priority of the interrupt is greater than the current priority level, exception processing
begins.
Exception processing occurs as follows. First, the processor makes an internal copy of the
SR. After the copy is made, the processor state bits in the SR are changed—the S-bit is
set, establishing supervisor access level, and bits T1 and T0 are cleared, disabling
tracing. Priority level is then set to the level of the interrupt, and the processor fetches a
vector number from the interrupting device (CPU space $F). The fetch bus cycle is
classified as an interrupt acknowledge, and the encoded level number of the interrupt is
placed on the address bus.
If an interrupting device requests automatic vectoring, the processor generates a vector
number (25 to 31) determined by the interrupt level number.
If the response to the interrupt acknowledge bus cycle is a bus error, the interrupt is taken
to be spurious, and the spurious interrupt vector number (24) is generated.
The exception vector number, PC, and SR are saved on the supervisor stack. The saved
value of the PC is the address of the instruction that would have executed if the interrupt
had not occurred.