MOTOROLA
MC68349 USER'S MANUAL
4- 17
4.2.4.1 PROGRAMMABLE FEATURES. The chip select function supports the following
programmable features:
Four Programmable Chip Select Circuits
All four chip select circuits are independently programmable from the same list of
selectable features. Each chip select circuit has an individual base address register and
address mask register that contain the programmed characteristics of that chip select.
The base address register selects the starting address for the address block in 256-byte
increments. The address mask register specifies the size of the address block range.
The base address register V-bit indicates that the register information for that chip select
is valid. A global chip select allows address decode for a boot ROM before system
initialization occurs (see 4.2.4.2 Global Chip Select Operation).
Variable Block Sizes
The block size, starting from the specified base address, can vary in size from 256 bytes
up to 4 Gbytes in 2n increments. The specified base address must be on a multiple of
the block size. The block size is specified in the address mask register.
8-, 16-. and 32-Bit Ports Supported
The 8-bit ports are accessible on both odd and even addresses when connected to
D31–D24. The 16-bit ports can be accessed as odd bytes, even bytes, or even words
when connected to D31–D16. The 32-bit ports can be accessed as odd or even bytes,
odd or even words, or odd or even longwords. The port size is specified by the PS bits
in the address mask register.
Write Protect Capability
The WP bit in each base address register can restrict write access to its range of
addresses.
Fast Termination Option
Programming the EDS bit (base address register) and the DD1 and DD2 bits (address
mask register) to a value of 111 selects the fast termination option. The fast termination
option causes the chip select to terminate the cycle by asserting the internal DSACK≈
early, providing a two-cycle external access.
Internal DSACK≈ Generation for External Accesses with Programmable Wait States
DSACK≈ can be generated internally with up to six wait states for a particular device
using the EDS bit in the base address register along with the DDx bits in the address
mask register.
Full 32-Bit Address Decode with Address Space Checking
The FC bits in the base address register and FCM bits in the address mask register are
used to select address spaces for which the chip selects will be asserted.