INDEX- 2
MC68349 USER’S MANUAL
MOTOROLA
Bypass Register, 9-11
— C —
Cache Coherency, 5-9
Cache Miss, 5-8
Calculate Effective Address Timing Table, 5-93
Call User Code Command (CALL), 5-59, 5-66, 5-75
Change of Flow, 5-82
Channel
Control Register (CCR), 7-24
Example Configuration Code, 7-39
Mode Register, 8-13
Status Register, 7-28, 8-8, 8-10
Termination, 7-20
Character Mode, 8-13
Chip-junction Temperature, 11-2
Chip Select, 1-8, 4-16
Address Mask Register, 3-4
Global Chip Select, 4-18
Output Signals, 2-6, 3-52
Programmable Features, 4-17
CLKOUT Signal, 10-7
Clock Control Circuits, 4-16
Clock Operating Modes, 4-9
Clock Synthesizer Control Register (SYNCR), 4-32
Clock Synthesizer, 1-8, 4-9, 10-1
Clock-Select Register (CSR), 8-6, 8-20
Code Compatibility, 5-13, 5-18
Command
Call User Code (CALL), 5-75
Condition Code Register, 5-15
Control Register (CCR), 7-4
Dump Memory Block (DUMP), 5-72
Fill Memory Block (FILL), 5-73
Future 5-78
ILLEGAL, 5-78
No Operation (NOP), 5-77
Read A/D Register (RAREG/DREG), 5-67
Read Memory Location (READ), 5-70
Read System Register (RSREG), 5-68
Registers (CR), 8-10, 8-22
Reset Peripherals (RST), 5-77
Resume Execution (GO), 5-74
Sequence Diagram, 5-65
Write A/D Register (WAREG/WDREG), 5-67
Write Memory Location (WRITE), 5-71
Write System Register (WSREG), 5-69
Conditional Branch Instruction Timing Table, 5-102
Configurable Instruction Cache (CIC), 1-5, 3-8, 5-1,
5-6, 6-1
Instruction Cache Mode, 5-7
Programmer's Model, 5-10
Replacement Algorithm, 5-9
Control Instruction Table, 5-103
CPU030, 1-4, 5-1
CPU32, 5-1, 5-27
CPU32+, 1-4, 5-1
Architecture ,5-13
Block Diagram, 5-4
Features, 5-3
Instruction set, 5-16
Privilege Levels, 5-13, 5-26
Programming Model, 5-13
Registers, 5-15
Serial Logic, 5-59
Stack Frames, 5-50
CPU Space, 3-32
Crystal, 8-5
CTS≈ Signals, 2-13, 8-7, 8-11
Current Instruction Program Counter, 5-52, 5-58
Cycle
Breakpoint Acknowledge, 3-33
Bus, 3-2
Fast Termination, 3-22
Interrupt Acknowledge, 3-41
Interrupt Acknowledge Bus Cycle, 3-38
Low Power Stop (LPSTOP) Broadcast, 3-34
Read cycle, 3-4, 3-8, 3-23, 3-39
Read-Modify-Write Cycle, 3-30
Show Cycles, 3-57
Steal Request Mode, 7-5
Write Cycle, 3-4, 3-8, 3-28
— D —
Data
Bus, 2-5, 3-1, 3-4, 3-23
Holding Register (DHR), 7-12, 7-35
Registers, 5-15
DBcc instruction, 5-4
DC Electrical Specifications, 11-5
Destination Address Register (DAR), 7-29
Destination Function Code Register (DFC), 5-15
Deterministic Opcode Tracking, 5-53, 5-54, 5-78
Development Serial Clock Input 2-10