11/3/95
SECTION 1: OVERVIEW
UM Rev 1
MOTOROLA
MC68349 USER'S MANUAL
ix
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
5.6.3.1.2
Type II—Prefetch, Operand, RMW, and MOVEP Faults ............ 5-45
5.6.3.1.3
Type III—Faults During MOVEM Operand Transfer .................. 5-46
5.6.3.1.4
Type IV—Faults During Exception Processing........................... 5-46
5.6.3.2
Correcting a Fault........................................................................... 5-47
5.6.3.2.1
Type I—Completing Released Writes via Software ................... 5-47
5.6.3.2.2
Type I—Completing Released Writes via RTE........................... 5-47
5.6.3.2.3
Type II—Correcting Faults via RTE............................................ 5-48
5.6.3.2.4
Type III—Correcting Faults via Software .................................... 5-48
5.6.3.2.5
Type III—Correcting Faults by Conversion and Restart ............. 5-48
5.6.3.2.6
Type III—Correcting Faults via RTE........................................... 5-49
5.6.3.2.7
Type IV—Correcting Faults via Software ................................... 5-49
5.6.4
CPU32+ Stack Frames ..................................................................... 5-50
5.6.4.1
Four-Word Stack Frame ................................................................ 5-50
5.6.4.2
Six-Word Stack Frame ................................................................... 5-50
5.6.4.3
BUS ERROR Stack Frame ............................................................ 5-50
5.7
Development Support ........................................................................... 5-53
5.7.1
CPU32+ Integrated Development Support ........................................ 5-53
5.7.1.1
Background Debug Mode (BDM) Overview ................................... 5-54
5.7.1.2
Deterministic Opcode Tracking Overview ...................................... 5-54
5.7.1.3
On-Chip Hardware Breakpoint Overview ....................................... 5-55
5.7.2
Background Debug Mode .................................................................. 5-55
5.7.2.1
Enabling BDM ................................................................................ 5-56
5.7.2.2
BDM Sources ................................................................................. 5-56
5.7.2.2.1
External BKPT Signal. ................................................................ 5-56
5.7.2.2.2
BGND ......................................................................................... 5-56
5.7.2.2.3
Double Bus Fault. ....................................................................... 5-56
5.7.2.3
Entering BDM ................................................................................. 5-57
5.7.2.4
Command Execution. ..................................................................... 5-57
5.7.2.5
BDM Registers ............................................................................... 5-57
5.7.2.5.1
Fault Address Register (FAR) .................................................... 5-57
5.7.2.5.2
Return Program Counter (RPC) ................................................. 5-57
5.7.2.5.3
Current Instruction Program Counter (PCC). ............................. 5-58
5.7.2.6
Returning from BDM ...................................................................... 5-59
5.7.2.7
Serial Interface ............................................................................... 5-59
5.7.2.7.1
CPU Serial Logic ........................................................................ 5-60
5.7.2.7.2
Development System Serial Logic ............................................. 5-62
5.7.2.8
Command Set ................................................................................ 5-63
5.7.2.8.1
Command Format ...................................................................... 5-63
5.7.2.8.2
Command Sequence Diagram ................................................... 5-64
5.7.2.8.3
Command Set Summary ............................................................ 5-66
5.7.2.8.4
Read A/D Register ..................................................................... 5-67
5.7.2.8.5
Write A/D Register...................................................................... 5-67