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INDEX- 6
MC68349 USER’S MANUAL
MOTOROLA
User Privilege Level, 5-27
Privilege Violation, 5-38, 5-50
Processing States, 5-26
Program Counter (PC), 4-39, 5-2, 5-15, 5-50, 5-52
Programming Model, 4-21
— Q —
Quad Data Memory Module, 1-5, 5-1, 5-8, 5-10, 6-1
Application Areas, 6-2
Base Address Registers, 6-4
Programming Model, 6-2
— R —
R/ W 2-7, 3-2, 5-63
RMC Signal, 2-9, 3-2, 3-53
RTSA, RTSB Signals, 2-13
RxDA, RxDB Signals, 2-12
R≈RDYA Signals, 2-12
Read
A/D Register Command, 5-67
Byte, 3-23
Dual-Address Read Cycle, 7-12
Long-Word,3-23
Memory Location Command, 5-70
Read Cycle, 3-4, 3-8, 3-23, 3-39
Serial Module, 8-17
Single-Address Source Cycle, 7-7
System Register Command, 5-57, 5-68
Word, 3-23
Read-Modify-Write
Cycle, 3-30, 5-43
Faults, 5-45
Tming, 3-30
Receiver
Block Diagram, 8-8
Break Condition, 8-12
Buffer (RB), 8-39
Timing, 8-11
Register(s)
Autovector Register (AVR), 4-5, 4-26
Auxiliary Control Register, (ACR) 8-20
Background Debug Mode, 5-57
Boundary Scan Register, 9-3
Byte Transfer Count Register (BTC), 7-15, 7-24
Channel Control Register (CCR), 7-24
Channel Mode Register (MR1), 8-13
Channel Status Register, 7-28, 8-7, 8-10
Clock Synthesizer Control Register (SYNCR),
4-32
Clock-Select Register (CSR), 8-6, 8-8, 8-20
Command Register (CR), 8-10, 8-22
Condition Code Register (CCR), 5-15
Control Register (CCR), 7-4
CPU32+, 5-15
Current Instruction Program Counter, 5-58
Data Holding Register (DHR), 7-12
Destination Address Register (DAR), 7-29
Destination Function Code (DFC), 5-15
DMA Module, 7-22
Fault Address, 5-57
Function Code Register (FCR), 7-30
Identification Register (IDR), 4-26
Input Port Change Register (IPCR), 8-25
Input Port Register (IP), 8-26
Instruction Register, 5-78
Interrupt Enable Register (IER), 8-4, 8-7, 8-27
Interrupt Level Register (ILR), 8-28
Interrupt Register (INTR), 7-31
Interrupt Status Register (ISR), 8-3, 8-7, 8-8,
8-28
Interrupt Vector Register (IVR), 8-17, 8-30
Mode Registers, 8-33, 8-35
Module Base Address Register (MBAR), 3-38,
4-2, 4-23, 7-23, 8-18
Module Configuration Register (MCR), 4-3,
4-24, 5-11, 6-3, 7-22, 7-32, 8-31
Output Port Control Register (OPCR), 8-38
Output Port Data Register (OP), 8-6, 8-37
Periodic Interrupt Control Register (PICR), 4-7
Periodic Interrupt TImer Register (PITR), 4-7,
4-31
Port A Data DIrection Register (DDRA), 4-38
Port A Data Register (PORTA), 4-38
Port A Pin Assignment Registers, 4-37
Port B Data Direction Register (DDRB), 4-39
Port B Data Register (PORTB), 4-39
Port B Pin Assignment Register (PPARB), 4-5,
4-38
Program Counter (PC), 5-15
QDMM Base Address Registers (QBARx), 6-4
Receiver Buffer (RB), 8-39
Reset Status Register (RSR), 4-3, 4-27
SIM49 Registers, 4-21, 4-40