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11/3/95
SECTION 1: OVERVIEW
UM Rev 1
MOTOROLA
MC68349 USER'S MANUAL
vii
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
4.3.2.5
Software Interrupt Vector Register (SWIV) .................................... 4-28
4.3.2.6
System Protection Control Register (SYPCR) ............................... 4-28
4.3.2.7
Periodic Interrupt Control Register (PICR)..................................... 4-30
4.3.2.8
Periodic Interrupt Timer Register (PITR) ....................................... 4-31
4.3.2.9
Software Service Register (SWSR) ............................................... 4-31
4.3.3
Clock Synthesizer Control Register (SYNCR) ................................... 4-32
4.3.4
Chip Select Registers ........................................................................ 4-33
4.3.4.1
Base Address Registers ................................................................ 4-33
4.3.4.2
Address Mask Registers ................................................................ 4-35
4.3.4.3
Chip Select Registers Programming Example ............................... 4-36
4.3.5
External Bus Interface Control........................................................... 4-37
4.3.5.1
Port A Pin Assignment Register 1 (PPARA1) ................................ 4-37
4.3.5.2
Port A Pin Assignment Register 2 (PPARA2) ................................ 4-37
4.3.5.3
Port A Data Direction Register (DDRA) ......................................... 4-38
4.3.5.4
Port A Data Register (PORTA) ...................................................... 4-38
4.3.5.5
Port B Pin Assignment Register (PPARB) ..................................... 4-38
4.3.5.6
Port B Data Direction Register (DDRB) ......................................... 4-39
4.3.5.7
Por t B Data Register (PORTB, PORTB1) ................................ ..... 4-39
4.4
MC68349 Initialization Sequence.......................................................... 4-39
4.4.1
Startup ............................................................................................... 4-39
4.4.2
SIM49 Module Configuration ............................................................. 4-40
4.4.3
SIM49 Example Configuration Code ................................................. 4-42
SECTION 5
CPU030
5.1
CPU32+ Overview................................................................................. 5-1
5.1.1
CPU32+ Features .............................................................................. 5-3
5.1.2
Virtual Memory .................................................................................. 5-3
5.1.3
Loop Mode Instruction Execution ...................................................... 5-4
5.1.4
Vector Base Register......................................................................... 5-5
5.1.5
Exception Handling............................................................................ 5-5
5.1.6
Addressing Modes ............................................................................. 5-6
5.2
Configurable Instruction Cache Overview ............................................. 5-6
5.2.1
CIC Modes......................................................................................... 5-7
5.2.1.1
Instruction Cache Mode ................................................................. 5-7
5.2.1.2
SRAM Mode................................................................................... 5-10
5.2.2
Programmer's Model ......................................................................... 5-10
5.2.2.1
Module Configuration Register (MCR) ........................................... 5-11
5.2.2.2
SRAM Base Address Registers 3–0 (BADDR3–0) ........................ 5-12
5.3
Architecture Summary ........................................................................... 5-13
5.3.1
Programming Model .......................................................................... 5-13
5.3.2
Registers ........................................................................................... 5-15