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11/3/95
SECTION 1: OVERVIEW
UM Rev 1
MOTOROLA
MC68349 USER'S MANUAL
xxi
LIST OF TABLES
Table
Page
Number
Title
Number
1-1
MC68349-Related Documentation ............................................................... 1-10
2-1
Signal Index ................................................................................................. 2-2
2-2
Address Space Encoding ............................................................................. 2-5
2-3
SIZx Signal Encoding ................................................................................... 2-8
2-4
DSACK≈ Encoding ....................................................................................... 2-8
2-5
Signal Summary ........................................................................................... 2-14
3-1
Address Space Encoding ............................................................................. 3-3
3-2
DSACK≈ Encoding ....................................................................................... 3-5
3-3
SIZx Encoding .............................................................................................. 3-7
3-4
Address Offset Encoding ............................................................................. 3-8
3-5
Data Bus Requirements for Read Cycles .................................................... 3-9
3-6
MC68349 Internal to External Data Bus Multiplexer—Write Cycle .............. 3-10
3-7
Memory Alignment and Port Size................................................................. 3-20
3-8
DSACK≈ , BERR , and HALT Assertion Results ............................................ 3-44
4-1
Clock Operating Modes ............................................................................... 4-9
4-2
System Frequencies from 32.768-kHz Reference ....................................... 4-14
4-3
Clock Control Signals ................................................................................... 4-16
4-4
D31, D30 Encoding for Global Chip Select Size .......................................... 4-18
4-5
Port A Pin Assignment Register ................................................................... 4-18
4-6
Port B Pin Assignment Register ................................................................... 4-19
4-7
SHENx Control Bits ..................................................................................... 4-25
4-8
Deriving Software Watchdog Timeout .......................................................... 4-29
4-9
BMTx Encoding ............................................................................................ 4-29
4-10
PIRQL Encoding........................................................................................... 4-30
4-11
EDS and DDx Encoding ............................................................................... 4-36
4-12
PSx Encoding............................................................................................... 4-36
5-1
Instruction Set .............................................................................................. 5-17
5-2
Standard Usage Entries ............................................................................... 5-19
5-3
Compressed Table Entries........................................................................... 5-21
5-4
8-Bit Independent ......................................................................................... 5-22
5-5
Exception Vector Assignments .................................................................... 5-29
5-6
Exception Priority Groups ............................................................................ 5-32
5-7
Tracing Control ............................................................................................. 5-38