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參數(shù)資料
| 型號(hào)： | MB86860 |
| 廠商： | FUJITSU LTD |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 200 MHz, RISC PROCESSOR, PBGA352 |
| 封裝： | PLASTIC, BGA-352 |
| 文件頁(yè)數(shù)： | 9/70頁(yè) |
| 文件大?。?/td> | 1395K |
| 代理商： | MB86860 |
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Specifications subject to changes without prior notice
18
MB86860 SPARClite
3.9. IDCCR : Idle Cycle Control Register
Performs automatic Idle Cycle insertion settings for CS0# area access.
31
4
3
1
0
Reserved
IDCC
IDCE
Address: 0x80000440 (ASI=04)
Reset State: 0x00000000
Figure 3-11 IDCCR Register
bit31-4:
Reserved
bit3-1:
Idle Cycle Count [IDCC]
bit0:
Idle Cycle Enable [IDCE]
3.10. SDCFG : SDRAM Configuration Register
This register decides such SDRAM operating modes as CAS Latency, SDRAM Type, Bus Size etc.
31
13
12
11
9 8
5
4
3
2
1
0
Reserved
RG
CL
ST
BS
PRC
SPC
SPE
SE
Address: 0x80000800 (ASI=04)
Reset State: 0x00000400
Figure 3-12 SDCFG Register
*Burst Type is sequential fixed.
bit31-13:
Reserved
bit12:
Registered Mode [RG] ---- This bit is WRITE ONLY. i.e., the bit can not be read out.
bit1-9:
CAS Latency [CL]
bit8-5:
SDRAM Type [ST]
bit4:
Bus Size [BS]
bit3:
Precharge Control [PRC
bit2:
SDRAM Parity Control [SPC
bit1:
SDRAM Parity Enable [SPE]
bit0:
SDRAM
Enable
[SE]
Table 3-6 CAS
Table 3-8 SDRAM Type
Latency
Table 3-7 Bus Size
ST
SDRAM Type
0000
Reserved
0001
16Mbit 2bank x 1M x 8bit
0010
16Mbit 2bank x 512k x 16bit
0011
Reserved
0100
Reserved
0101
64Mbit 4bank x 2M x 8bit
0110
64Mbit 4bank x 1M x 16bit
0111
64Mbit 4bank x 512k x 32bit
1000
Reserved
1001
Reserved( 128Mbit 4bank x 4M x 8bit )
1010
Reserved( 128Mbit 4bank x 2M x 16bit )
1011
Reserved
1100
Reserved
1101
Reserved( 256Mbit 4bank x 8M x 8bit )
1110
Reserved( 256Mbit 4bank x 4M x 16bit )
1111
Reserved
CL
CAS
Latency
000
Reserved
001
1
010
2
011
3
100
Reserved
101
Reserved
110
Reserved
111
Reserved
BS
Bus Size
0
32bit
1
64bit
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